Abstract: A display method and a display device are disclosed herein.

Abstract: Methods for compensating for warpage in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming a buffer layer on the epitaxial layer and forming a compensating layer on the buffer layer; forming a buffer layer on the semiconductor substrate and forming a compensating layer on the buffer layer; and forming grooves in the epitaxial layer.

Abstract: A color sequential image method for displaying images using two color fields includes analyzing and sorting percentages of a plurality of colors constituting an input color image, in which a first color possesses a most percentage, a second color possesses a middle percentage, and a third color possesses a third percentage. The method further includes forming a first color field image according to the first color and the third color, and a second color field image according to the second color and the third color.

Abstract: A method includes generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also includes searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further includes displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration.

Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.

Abstract: A method comprises generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also comprises searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further comprises displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration. The method additionally comprises displaying a layout of the IC based on a determination that the schematic passed a design rule check, the displayed layout of the IC including the selected configuration of the circuit component, the selected configuration being displayed in the layout having the assigned color scheme.

Abstract: Programming hardware registers using a pipelined register bus, and related methods, systems, and apparatuses are disclosed. In one aspect, a method for communicating over a register bus comprises initiating, at a register bus master, a request comprising an address, and passing the request from the register bus master to a first register bus slave of a processor module via a register bus. The method further comprises decoding the address at a module core of the processor module, and determining whether the address corresponds to the processor module. The method also comprises, responsive to determining that the address corresponds to the processor module, processing the request by the module core, and passing the same request as-is to a second register bus slave. The method additionally comprises, responsive to determining that the address does not correspond to the processor module, passing the same request as-is to the second register bus slave.

Abstract: A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose.

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract: A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC.

Abstract: A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Abstract: A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An operation of at least one first circuit element in the first substrate is simulated based on the first environment temperature.

Abstract: A method comprises generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also comprises searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further comprises displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration. The method additionally comprises displaying a layout of the IC based on a determination that the schematic passed a design rule check, the displayed layout of the IC including the selected configuration of the circuit component, the selected configuration being displayed in the layout having the assigned color scheme.

Abstract: One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments.

Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose.

Abstract: A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An operation of at least one first circuit element in the first substrate is simulated based on the first environment temperature.

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract: A method for updating a basic input/output system of a server is disclosed. The method can be done by that of activating a customer end server; a BIOS initializing a network interface card; the customer end server linking a management end server; transmitting a product serial number of the customer end server and a version of the BIOS to the management end server for determination; if the management end server determines that the BIOS does need to be updated, the customer end server downloading the latest BIOS; the customer end server directly accessing a flash memory in the customer end server via an access program code in the BIOS, so as to burn the latest BIOS into the flash memory. Hence the customer end server automatically updates the BIOS therein while in a POST (power-on self-test) without entering into an operating system.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.