Patents by Inventor Chi-Wen Chang

Chi-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8957506
    Abstract: A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: February 17, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yueh-Liang Hsu, Chi-Wen Chang
  • Patent number: 8701055
    Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Wen-Shen Chou
  • Publication number: 20130342430
    Abstract: A color sequential image method for displaying images using two color fields includes analyzing and sorting percentages of a plurality of colors constituting an input color image, in which a first color possesses a most percentage, a second color possesses a middle percentage, and a third color possesses a third percentage. The method further includes forming a first color field image according to the first color and the third color, and a second color field image according to the second color and the third color.
    Type: Application
    Filed: November 19, 2012
    Publication date: December 26, 2013
    Applicants: NATIONAL CHIAO TUNG UNIVERSITY, WISTRON CORP.
    Inventors: Yi-Pai Huang, Chi-Wen CHANG, Fang-Cheng LIN, Han-Ping SHIEH, Meng-Chao KAO, Hui-Chen LIN, Szu-Fen CHEN
  • Patent number: 8526752
    Abstract: An imaging system may include an image sensor and an image encoder that encodes images from the image sensor with fixed output sizes and frame rates. The image encoder may encode images from the image sensor into an image format such as a Joint Photographic Experts Group (JPEG) format. The image encoder may insert padding data between image blocks in the encoded data to compensate in real time for variations in the encoded size of an image. The amount of padding data inserted by the encoder may be calculated to ensure the encoded image has a file size close to, but not greater than, the required fixed output size. If needed, the encoder may add additional padding data after the image blocks are encoded in a blanking period before a subsequent image is encoded so that the final size of the encoded image is equal to the required output size.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Aptina Imaging Corporation
    Inventors: Sheng Lin, Adam Zerwick, Kai Yau Mok, Chi-Wen Chang
  • Publication number: 20120044375
    Abstract: An imaging system may include an image sensor and an image encoder that encodes images from the image sensor with fixed output sizes and frame rates. The image encoder may encode images from the image sensor into an image format such as a Joint Photographic Experts Group (JPEG) format. The image encoder may insert padding data between image blocks in the encoded data to compensate in real time for variations in the encoded size of an image. The amount of padding data inserted by the encoder may be calculated to ensure the encoded image has a file size close to, but not greater than, the required fixed output size. If needed, the encoder may add additional padding data after the image blocks are encoded in a blanking period before a subsequent image is encoded so that the final size of the encoded image is equal to the required output size.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Inventors: Sheng Lin, Adam Zerwick, Kai Yau Mok, Chi-Wen Chang
  • Publication number: 20100219518
    Abstract: A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires.
    Type: Application
    Filed: October 14, 2009
    Publication date: September 2, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yueh-Liang Hsu, Chi-Wen Chang
  • Patent number: 7141867
    Abstract: The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: November 28, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Chi-Wen Chang
  • Publication number: 20060001136
    Abstract: The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Inventors: Su Tao, Chi-Wen Chang
  • Publication number: 20050218499
    Abstract: A method for manufacturing a plurality of leadless semiconductor packages is disclosed. A provided metal carrier has a plurality of packaging units with contact pads and a plurality of separating streets between the packaging units. A plurality of chips are disposed on the corresponding packaging units of the metal carrier and are electrically connected to the contact pads. A plurality of encapsulants are formed on the corresponding packaging units to encapsulate the chips but exposing the separating streets. After the metal carrier is etched away, the encapsulants connected by mold runner bars can be easily separated without sawing or punching.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Inventors: Chi-Wen Chang, Chao-Ming Tseng
  • Patent number: 5396584
    Abstract: Multi-bit image edge enhancement method and apparatus wherein a group of gradient mask matrices are applied to a "current matrix", wherein a TBAP (To Be Adjusted Pixel) is surrounded by neighboring pixels, to determine if the TBAP is at a location where a change of brightness occurs. From this matrix operation, a conclusion is derived as to the existence or non-existence of an edge and the direction of the brightness change. The current matrix and a predetermined number of previously evaluated and yet to be evaluated pixels are then compared to a set of reference bit patterns which depict possible segment changes to be corrected. If the result indicates that the TBAP is on an edge of a changing edge segment, a corresponding code will be generated to modify the TBAP to enhance the smoothness of a segment transition.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: March 7, 1995
    Assignee: Destiny Technology Corporation
    Inventors: Tse-Han Lee, Ling-Yi Liu, Che-Hung Hu, Chi-Wen Chang