Abstract: An organic light emitting diode (OLED) display panel is provided. The OLED display panel includes a substrate, a conductive layer, an active matrix pixel array and several thin film transistors (TFTs). The conductive layer having several openings is disposed above the substrate. The active matrix pixel array having several pixels is disposed above the conductive layer. Each pixel has a display region and a non-display region. The display regions correspond to the openings. The TFTs are correspondingly disposed inside the pixels and correspondingly positioned inside the non-display regions. Each TFT includes a channel layer, a source, a drain and a gate. The channel layer is disposed above the conductive layer. The source and the drain are disposed above channel layer and respectively contact with the two opposite sides of the channel layer. The gate is disposed above the channel layer and positioned between the source and the drain.

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract: An electric insect trap includes a base, an insect attracting unit provided on the base, a high voltage grid unit provided on the base and disposed to surround the insect attracting unit, a detector unit coupled electrically to the high voltage grid unit and operable so as to generate a detector signal corresponding to an insect-electrocuting state of the high voltage grid unit, and an indicator unit coupled electrically to the detector unit and operable so as to indicate number of insects electrocuted by the high voltage grid unit based on the detector signal received from the detector unit.

Abstract: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.

Abstract: A display and the thin-film-transistor discharge method therefore are used for providing a dual-gate thin film transistor to drive the electroluminescent element to emit light. While the thin film transistor (TFT) is discharged, an electric field is formed between the top-gate and the bottom-gate. The electric field is for improving the electric discharge effect at the channel of the TFT, and the magnitude of the applied electric field corresponds to the magnitude of the pixel voltage.

Abstract: A method for manufacturing a thin film transistor of the invention comprises steps of: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a polysilicon layer on the gate insulating layer; forming an etching-stop layer on the polysilicon layer and corresponding to the gate electrode; forming a heavily doped polysilicon layer on the etching-stop layer and the polysilicon layer, the heavily doped polysilicon layer exposing a part of the etching-stop layer; and forming a source electrode and a drain electrode on the heavily doped polysilicon layer, and the source and drain electrode relatively positioned above the two sides of the gate electrode.

Abstract: An electric plug includes a housing which has front and rear walls, a fuse-receiving space, and a first aperture provided in the front wall. First and second conductive members are mounted inside the housing and project outwardly from the front wall. The second conductive member has a first fuse contact part extending into the fuse-receiving space. First and second wire conductors extend into the housing through the rear wall. The second wire conductor has a second fuse contact part extending into the fuse-receiving space. A first fuse member is disposed in the fuse-receiving space and contacts first and second fuse contact parts of the second conductive member and wire conductor. A cover plate covers the first aperture and has two insert holes for outward extension of the first and second conductive members.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

Abstract: An electrical socket includes a sliding rail unit and a receptacle unit disposed slidably on the sliding rail unit. The receptacle unit includes a base and a receptacle seat mounted rotatably on the base. The receptacle seat is rotatable on the base between a conducting position, where the receptacle unit is retained on the sliding rail unit, and a non-conducting position, where the receptacle unit is removable from the sliding rail unit.

Abstract: A power control device includes a power coupler that includes a housing, a power input unit, a socket receptacle, and a control unit. The power input unit is mounted on the housing of the power coupler, and is connected electrically and removably to a commercial alternating current power source. The socket receptacle is mounted on the housing of the power coupler, and is adapted to be connected electrically and removably to an electrical appliance. The control unit is coupled between the power input unit and the socket receptacle, and is responsive to a wireless control signal for controlling electrical connection between the power input unit and the socket receptacle.

Abstract: A power supply connector includes a housing and a prong unit. The housing has opposite first and second housing walls, a peripheral wall extending between the first and second housing walls to define an accommodation space, a prong slot having a first slot section formed in the peripheral wall and a second slot section formed in the first housing wall, and a pair of slide rails disposed on opposite sides of the prong slot. The prong unit includes a prong base disposed in the accommodation space, and two conductive prongs mounted on the prong base. The prong base is slidable along the slide rails so that the prongs extend out of the housing through the first slot section or the second slot section of the prong slot.

Abstract: A thin film transistor is characterized by having an island-in structure having a semiconductor layer with a channel region, a bottom heavily-doped semiconductor layer, and a top heavily-doped semiconductor layer. The bottom heavily-doped semiconductor layer is positioned on two opposite sides of the surface of the semiconductor layer beyond the channel region. The top heavily-doped semiconductor layer, positioned on the bottom heavily-doped semiconductor layer, covers two opposite side walls of the bottom heavily-doped semiconductor layer and the semiconductor layer so that current leakage from the drain electrode to the source electrode is prevented.

Abstract: An electric wire includes a core unit including at least two sheathed wires that are helically twisted together about a central axis, and a sheath surrounding the core unit. Each of the sheathed wires includes an insulation layer and a conductive core surrounded by the insulation layer. The sheath is helically twisted about the central axis, and has an outer layer that is helically twisted about the central axis and that has a cross-section which includes a plurality of first crest regions and a plurality of second crest regions that are alternately disposed with the first crest regions. Each of the first crest regions cooperates with an adjacent one of the crest regions to define a trough region therebetween. The distance from each of the first crest regions to the central axis is different from that from each of the second crest regions to the central axis.

Abstract: An electric wire includes a core unit, and a sheath surrounding the core unit. The sheath includes an inner layer surrounding the core unit, and a transparent outer layer surrounding the inner layer. The outer layer has a cross-section including a plurality of first crest regions, and a plurality of second crest regions that are alternately disposed with the first crest regions. Each of the first crest regions cooperates with an adjacent one of the second crest regions to define a trough region therebetween. Each of the first crest regions has a thickness less than that of each of the second crest regions.

Abstract: An electrical switch device includes a housing, a power input unit, a phone jack, a socket receptable, and a switching circuit. The power input unit extends from the housing, and is coupled to a commercial alternating current power source. The phone jack is mounted on the housing, and is coupled to a phone line. The socket receptacle is mounted on the housing, and is coupled to an electrical load. The switching circuit is mounted in the housing, includes a switch and a switch actuator. The switch is coupled between the power input unit and the socket receptacle. The switch actuator is coupled between the phone jack and the switch, and is operable so as to receive a control signal from a calling party through the phone line, and so as to actuate the switch in response to the control signal.

Abstract: An IP telephony apparatus provides simultaneous SIP communication for multiple IP phones and a method is proposed for the same. The IP telephony apparatus comprises a network connection port connected to a network; a plurality of telephone connection ports connected to a plurality of telephone sets; a voice codec unit connected to the telephone connection ports and used for converting a voice signal to a digital voice packet and for converting a digital voice packet to a voice signal; and an IP telephony allocation unit connected to the network connection port and the plurality of telephone connection ports. The IP telephony allocation unit creates an SIP control block containing an SIP call-leg for a local SIP number, and allocates the SIP control block to a destination telephone set according to the SIP call-leg, whereby the telephone sets have bi-directional digital voice packet transmission with a remote SIP number.

Abstract: An automatic setting method for ATM network is used in an information device for automatic connecting to an ATM network of an ISP office. At first an automatic configuration table is provided and includes a plurality sets of setting parameters of virtual path identifier (VPI)/virtual channel identifier (VCI) and encapsulation capacity for a plurality of default ISP offices. A user tries connection to the ISP office by selecting one set of the setting parameters as a connecting parameter to the ISP office and receives a reply message from the ISP office. The user selects another one set of the setting parameters as a connecting parameter to the ISP office when the connection fails and tries again until the connection to the ISP office successes.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

Abstract: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.