Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal Gate Stack Having TaAlCN Layer
    Publication number: 20200090938
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 19, 2020
    Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LIU
  • FinFET Structure with Different Fin Heights and Method for Forming the Same
    Publication number: 20200083091
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 12, 2020
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Vertical Gate All Around (VGAA) Devices and Methods of Manufacturing the Same
    Publication number: 20200075742
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 5, 2020
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Antifuse Array and Method of Forming Antifuse Using Anodic Oxidation
    Publication number: 20200051988
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Stacked Gate-All-Around FinFET and Method Forming the Same
    Publication number: 20200044088
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200035564
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Semiconductor Device and Manufacturing Method Thereof
    Publication number: 20200027963
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Strained nanowire CMOS device and method of forming
    Patent number: 10535732
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Interconnection Structure, Fabricating Method Thereof, and Semiconductor Device Using the Same
    Publication number: 20200013719
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE
    Publication number: 20200013869
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Semiconductor Device and Method of Forming the Same
    Publication number: 20200006498
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Metal gate scheme for device and methods of forming
    Patent number: 10522640
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • FinFET structure with different fin heights and method for forming the same
    Patent number: 10504770
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Semiconductor device and method of forming the same
    Patent number: 10505001
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Semiconductor device with transition metal dichalocogenide hetero-structure
    Patent number: 10505052
    Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 10, 2019
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • FinFET with sloped surface at interface between isolation structures
    Patent number: 10504787
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Antifuse array and method of forming antifuse using anodic oxidation
    Patent number: 10504907
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 10, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Devices including gate spacer with gap or void and methods of forming the same
    Patent number: 10505022
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20190363191
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Vertical tunneling field-effect transistor cell and fabricating the same
    Patent number: 10490654
    Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu