Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297548
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20190148526
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20190148523
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Publication number: 20190148244
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • Publication number: 20190148555
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Publication number: 20190139829
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 9, 2019
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20190140070
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10283613
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an insulator material formed between each of the one or more fins; a dielectric layer formed on a first portion of the fin structure; a first electrode formed on the dielectric layer; spacers formed on sidewalls of the first electrode; and a second electrode formed on a second portion of the fin structure. The first and second portions are different. The second electrode includes a surface that is in direct contact with a surface of the spacers.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10283590
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20190131178
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 2, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20190123042
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20190123143
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20190123177
    Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20190123047
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20190123184
    Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • Publication number: 20190123211
    Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • Patent number: 10269982
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • Patent number: 10269966
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
  • Publication number: 20190097029
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Application
    Filed: October 15, 2018
    Publication date: March 28, 2019
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Publication number: 20190088757
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh