Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20190363191
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Vertical tunneling field-effect transistor cell and fabricating the same
    Patent number: 10490654
    Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • FINFETS with Wrap-Around Silicide and Method Forming the Same
    Publication number: 20190355850
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 21, 2019
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Metal gate stack having TaAlCN layer
    Patent number: 10483112
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Interconnection structure, fabricating method thereof, and semiconductor device using the same
    Patent number: 10483208
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Vertical gate all around (VGAA) devices and methods of manufacturing the same
    Patent number: 10483367
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Semiconductor device and manufacturing method thereof
    Patent number: 10468504
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    Publication number: 20190326437
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
  • FIELD-EFFECT TRANSISTORS HAVING CONTACTS TO 2D MATERIAL ACTIVE REGION
    Publication number: 20190326399
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: October 24, 2019
    Inventors: Ling-Yen YEH, Yee-Chia YEO, Chi-Wen LIU
  • Method of manufacturing a semiconductor device including a ternary alloy layer formed by a microwafe anneal process
    Patent number: 10453688
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 22, 2019
    Assignees: National Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chung-Chun Hsu, Wei-Chun Chi
  • Pressure sensing device
    Patent number: 10416031
    Abstract: A pressure sensing mat may include: a first substrate; a second substrate disposed opposite to the first substrate; a first electrode layer disposed on a side of the first substrate that faces the second substrate, the first electrode layer comprising a plurality of first electrode patterns; a second electrode layer disposed on a side of the second substrate that faces the first substrate, the second electrode layer comprising a plurality of second electrode patterns; and a spacer layer disposed between the first substrate and the second substrate and comprising a plurality of holes such that the first electrode patterns are configured to contact the second electrode patterns through the holes.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 17, 2019
    Assignee: MedicusTek, Inc.
    Inventors: Chia-Ming Hsu, Chung-Chih Lin, Chi Wen Liu, Chun Lin, Chao-Hung Chou
  • Method of fabricating a semiconductor device having modified profile metal gate
    Patent number: 10418456
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20190279939
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • 3D Capacitor and Method of Manufacturing Same
    Publication number: 20190252519
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Passivated and faceted for fin field effect transistor
    Patent number: 10381482
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • FINFETs with wrap-around silicide and method forming the same
    Patent number: 10355137
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Negative Capacitance Field Effect Transistor
    Publication number: 20190207035
    Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
  • Method of forming a fin structure of semiconductor device
    Patent number: 10340191
    Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Semiconductor device having stressor layer
    Patent number: 10340383
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 2, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • FinFET device and fabricating method thereof
    Patent number: 10326006
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng