Abstract: A method for executing vector iota (viota) operation is disclosed. The method includes fetching a viota instruction, decoding the viota instruction into multiple viota micro-operations (uops), computing a first element viota value of a respective viota uop, determining a respective last element viota value of the respective viota uop based on the first element viota value of the respective uop, and writing the respective last element viota value of the respective viota uop to an allocated physical register. Each viota uop of the multiple viota uops has multiple elements, and each element has a viota value corresponding to a sum of active mask bits of preceding elements of the viota uops. The multiple elements of each viota uop comprise at least a first element that has a starting bit position of a respective uop and a last element that has an ending bit position of the respective uop.

Abstract: The disclosure provides a plurality of particles. Each particle may include a material comprising 0.95 to 1.30 mole fraction Li, at least 0.60 and less than 1.00 mole fraction Co, up to 10,000 ppm Al, 1.90 to 2.10 mole fraction O, and up to 0.30 mole fraction M, where M is at least one element selected from B, Na, Mg, P, Ti, Ca, V, Cr, Fe, Mn, Ni, Cu, Zn, Al, Sc, Y, Ga, Zr, Ru, Mo, La, Si, Nb, Ge, In, Sn, Sb, Te, and Ce. Each particle may also include a surface composition comprising a mixture of LiF and a metal fluoride. An amount of fluorine (F) is greater than 0 and less than or equal to 5000 ppm. The metal fluoride comprises a material selected from the group consisting of AlF3, CaF2, MgF2, and LaF2. The surface composition may also include a metal oxide comprising a material selected from the group consisting of TiO2, MgO, La2O3, CaO, and Al2O3. An amount of the metal oxide is greater than 0 and less than or equal to 20000 ppm.

Abstract: The present invention relates to a sizing agent composition, a sizing agent, a carbon fiber covered with the sizing agent, and a composite material. The sizing agent composition includes a polyamic acid and an alkali agent. The alkali agent has a specific molecular weight, and there is a specific molar ratio between the polyamic acid and the alkali agent, such that emulsification stability of the polyamic acid and thermal stability of a sizing layer consisting of the sizing agent are enhanced, thereby increasing interlayer bonding strength in the composite material that is made by the carbon fiber covered with the sizing agent.

Abstract: A class of benzoxazinone derivatives and a preparation method therefor, specifically related to a compound shown in formula (II), or a stereoisomer or a pharmaceutically acceptable salt thereof.

Abstract: A contacting member of a contact probe for a probe system for performing a functionality test to a DUT includes a body, a contact tip, and a tip transition section between the body and the contact tip. A bottom side of the contacting member, which faces toward the DUT when testing the DUT, includes a lower surface at the body, a tip bottom surface at the contact tip, and a tip transition surface at the tip transition section. A contact end of the contact tip for contacting the DUT is located on a front side of the tip bottom surface. A rear side of the tip bottom surface and the lower surface have a height difference therebetween. The tip transition surface gradually changes in height from the lower surface to the rear side of the tip bottom surface. The contacting member has high precision and structural strength.

Abstract: Provided is a pharmaceutical composition including an effective amount of mesenchymal stem cell derived exosomes. Also provided is a use of the pharmaceutical composition for preserving cartilage tissue, promoting cartilage regeneration and repairing damaged joints, thereby preventing or treating joint disorders in a subject in need thereof.

Abstract: Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.

Abstract: A micro LED display panel is provided. The micro LED display panel includes a driving substrate and a plurality of bonding pads disposed on the driving substrate and spaced apart from each other. The micro LED display panel also includes a plurality of micro LED structures electrically connected to the bonding pads. Each micro LED structure includes at least one electrode disposed on the side of the micro LED structure facing the driving substrate. The electrode has a normal contact surface and a side contact surface. The normal contact surface faces the driving substrate, and the side contact surface is laterally connected to the corresponding bonding pad.

Abstract: A remote controller is provided. The remote controller includes a motion sensing circuit and a wireless communication circuit electrically connected to the motion sensing circuit. The motion sensing circuit determines whether or not a motion of the remote controller complies with one of multiple reference motions. When the motion of the remote controller complies with one of the reference motions, the wireless communication circuit is switched from a sleep state to a working state. The wireless communication circuit that is in the working state determines whether or not a received signal strength indication between the remote controller and a controlled device is greater than or equal to a strength threshold. When the received signal strength indication is less than the strength threshold, the wireless communication circuit is switched from the working state to the sleep state.

Abstract: A method for recommending a product, includes: providing product information having a product description, a main image, and a plurality of alternate images; for each alternate image: performing saliency segmentation to obtain a segment and a background, defining a segment bounding box enclosing the segment, extracting image feature from the segment bounding box, extracting textual feature from the product description, extracting main image feature from the main image, matching the image feature of the segment bounding box to the textual feature and the main image feature, and determining the alternate image as a qualified alternate image if the image feature of the segment bounding box matches the textual feature and the main image feature; and when a number of the qualified alternate image equals to or is greater than a threshold number, recommending the product to customers.

Abstract: A vibration detection device is used to execute a vibration detection method for detecting a vibrating touch pad. The vibration detection device includes a first detection module which has a first moving plate, a circuit board and a plurality of acceleration sensors. The first moving plate is movable relative to the vibrating touch pad. The circuit board is disposed on the first moving plate. The plurality of acceleration sensors is disposed on the circuit board as an array, and can abut against a plurality of measuring points on the vibrating touch pad when the first moving plate is moved close to the vibrating touch pad, so as to simultaneously detect a vibration feedback parameter generated from each of the plurality of acceleration sensors.

Abstract: A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.