Patents by Inventor Chi Wu

Chi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147108
    Abstract: A battery resistance measuring method, applied to a battery with a battery resistance, comprising: (a) acquiring charge variation of the battery for a measuring time interval; (b) acquiring a voltage difference between a first battery voltage and a second battery voltage for the measuring time interval, wherein the first battery voltage is a battery voltage with loading and the second battery voltage is a battery voltage without loading; and (c) computing a battery resistance according to the charge variation and the voltage difference, and updating the battery resistance to a battery resistance table of the battery. The above-mentioned steps (a), (b) and (c) may be performed by the electronic device, which can be a mobile electronic device such as a mobile phone or a plate computer.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Jia-You Chuang, Jui-Chi Wu, Kuan-Yu Chen
  • Publication number: 20250149439
    Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Hao Kuang, Tung-Heng Hsieh, Sheng-Hsiung Wang, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu
  • Patent number: 12290827
    Abstract: Systems and methods are provided for securement of parts. One embodiment is a method for securing a part during fabrication. The method includes forming an interference fit between a pin and a wall defining a hole, supporting a weight of the part with the interference fit, and rotating the part around an axis of the part while the weight of the part is supported.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 6, 2025
    Assignee: The Boeing Company
    Inventors: John Shinozaki, Jerry Deming Chungbin, Steven Kuan-chi Wu
  • Publication number: 20250133688
    Abstract: This disclosure provides a heat dissipation assembly and an electronic device. The heat dissipation assembly includes a first fan, a first fin assembly, a second fan, a second fin assembly, a vapor chamber and a heat dissipation sheet. The second fan has a second inlet, at least one second outlet and a side outlet. The at least one second outlet and the side outlet are in fluid communication with the second inlet. A direction of the side outlet directs toward the first fan. The vapor chamber is thermally coupled to the first fin assembly and the second fin assembly. The heat dissipation sheet is in thermal contact with a side of the vapor chamber, and located between the first fan and the second fan.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 24, 2025
    Applicants: MICRO-STAR INT’L CO., LTD., MSI ELECTRONIC (KUN SHAN) CO., LTD.
    Inventors: Chia-Ming CHANG, Ching-Chi WU
  • Publication number: 20250133759
    Abstract: A method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: April 24, 2025
    Inventors: Chun-Hsiu Chiang, Pei Ying Lai, Cheng-Hao Hou, Chi On Chui, Shan-Mei Liao, Hung-Chi Wu
  • Patent number: 12271654
    Abstract: An audio dose monitoring circuit includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: April 8, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu Wei Liu, Chi Wu, Chia Chun Hung
  • Patent number: 12266577
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Publication number: 20250105099
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Patent number: 12245345
    Abstract: A voice-activated light system that includes a microphone for receiving one or more voice commands (which may be referred to as a “voice microphone”), one or more light sources (such as LEDs) coupled to a controller and a light driver. The light driver is for driving the light sources and the controller is for detecting a voice command in order to control the mode of operation of the one or more light sources. The controller can have multiple control commands each for selecting a different mode of operation of the light source(s). The modes can be controlled by a common voice input term followed by a second voice command corresponding to a mode of operation of the light source. The system may include a second microphone which may be referred to herein as a “music microphone”. The commands can include “light show,” “slow pulse,” “steady on,” “blinking,” or “off”.
    Type: Grant
    Filed: February 8, 2024
    Date of Patent: March 4, 2025
    Assignee: Fourstar Group Inc.
    Inventor: Yu-Chi Wu
  • Patent number: 12237228
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20250056835
    Abstract: An integrated circuit structure includes a semiconductor substrate, first and second source/drain features, a gate dielectric layer, a gate electrode, a field plate electrode, first and second metal silicide layers, a dielectric layer, and a spacer. The gate electrode and the field plate electrode are over the gate dielectric layer and respectively vertically overlapping a well region and a drift region in the semiconductor substrate. A first sidewall of the field plate electrode faces the gate electrode. The first and second metal silicide layers are over the gate electrode and the field plate electrode, respectively. The dielectric layer has a first portion between the gate electrode and the first sidewall of the field plate electrode and a second portion below a bottom surface of the field plate electrode. The spacer is alongside a second sidewall of the field plate electrode and over the second portion of the dielectric layer.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Bo SHU, Yun-Chi WU
  • Patent number: 12223323
    Abstract: A method for executing vector iota (viota) operation is disclosed. The method includes fetching a viota instruction, decoding the viota instruction into multiple viota micro-operations (uops), computing a first element viota value of a respective viota uop, determining a respective last element viota value of the respective viota uop based on the first element viota value of the respective uop, and writing the respective last element viota value of the respective viota uop to an allocated physical register. Each viota uop of the multiple viota uops has multiple elements, and each element has a viota value corresponding to a sum of active mask bits of preceding elements of the viota uops. The multiple elements of each viota uop comprise at least a first element that has a starting bit position of a respective uop and a last element that has an ending bit position of the respective uop.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: February 11, 2025
    Assignee: SiFive, Inc.
    Inventors: Yueh Chi Wu, Nicolas Rémi Brunie
  • Patent number: 12208119
    Abstract: Provided is a pharmaceutical composition including an effective amount of mesenchymal stem cell derived exosomes. Also provided is a use of the pharmaceutical composition for preserving cartilage tissue, promoting cartilage regeneration and repairing damaged joints, thereby preventing or treating joint disorders in a subject in need thereof.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: January 28, 2025
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Dah-Ching Ding, Kun-Chi Wu, Yu-Hsun Chang
  • Patent number: 12210874
    Abstract: Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: January 28, 2025
    Assignee: SiFive, Inc.
    Inventor: Yueh Chi Wu
  • Patent number: 12199034
    Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao Kuang, Tung-Heng Hsieh, Sheng-Hsiung Wang, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu
  • Patent number: 12176424
    Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: D1056119
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: December 31, 2024
    Assignee: Fourstar Group Inc.
    Inventor: Yu-Chi Wu
  • Patent number: D1056120
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: December 31, 2024
    Assignee: Fourstar Group Inc.
    Inventor: Yu-Chi Wu
  • Patent number: D1066558
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: March 11, 2025
    Assignee: Fourstar Group Inc.
    Inventor: Yu Chi Wu
  • Patent number: D1072151
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: April 22, 2025
    Assignee: Fourstar Group Inc.
    Inventor: Yu Chi Wu