Patents by Inventor Chi Wu

Chi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515339
    Abstract: A display device has a display area and a peripheral area and includes data lines, scan lines, gate transmission lines, and sub-pixels. The data lines and the gate transmission lines extend from the peripheral area into the display area. The data lines located in the display area extend along a first direction. The scan lines are located in the display area and extend along a second direction intersecting the first direction. The gate transmission lines are electrically connected to the scan lines. One of the gate transmission lines includes first, second, and third wires located in the display area. The first and third wires extend along the first direction. The second wire extends along the second direction. The first, second and third wires are electrically connected in sequence. The third wire is electrically connected to one of the scan lines.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Au Optronics Corporation
    Inventors: Yueh-Chi Wu, Ti-Kuei Yu, Hung-Chia Liao, Shu-Wen Liao, Shiang-Lin Lian
  • Publication number: 20220375795
    Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
  • Patent number: 11508843
    Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
  • Publication number: 20220368738
    Abstract: A data sharing method includes logging in a first account through a communication interface by a first receiver for establishing a link between the first receiver and a server corresponding to the communication interface, logging in a second account through the communication interface by a second receiver for establishing a link between the second receiver and the server corresponding to the communication interface, and transmitting image data from a first transmitter to the second receiver through the first receiver and the server for sharing the image data. The first receiver is linked to a first display. The second receiver is linked to a second display. The image data is shared with the first display and the second display.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 17, 2022
    Applicant: BENQ CORPORATION
    Inventors: Chen-Chi Wu, Chin-Fu Chiang, Chia-Nan Shih, Lin-Yuan You, Jung-Kun Tseng, Chuang-Wei Wu
  • Publication number: 20220368955
    Abstract: A data sharing method includes providing a receiver and at least one transmitter, changing a first hardware registration identification code of the at least one transmitter to a second hardware registration identification code of a virtual camera device corresponding to at least one communication software program by the receiver, and using the virtual camera device for converting at least one image data signal transmitted from the at least one transmitter to video stream data supported by the at least one communication software program after the receiver receives the at least one image data signal.
    Type: Application
    Filed: January 25, 2022
    Publication date: November 17, 2022
    Applicant: BENQ CORPORATION
    Inventors: Chen-Chi Wu, Chia-Nan Shih, Chin-Fu Chiang, Chuang-Wei Wu, Jung-Kun Tseng
  • Patent number: 11501933
    Abstract: An electronic device has a keyboard with an internal membrane. The membrane has a set of strain gauges configured to respond to a key press, such as when a collapsible dome collapses into contact with the membrane. The strain gauges are connected in a half Wheatstone bridge configuration and are positioned on the membrane in order to limit effects of temperature and subtle flexure of the membrane. The strain gauges are also configured to magnify detection of a resistance differential when a keycap is pressed with sufficient force.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 15, 2022
    Assignee: APPLE INC.
    Inventors: Chia Chi Wu, Michael Vosgueritchian, Ming Gao, Nan Chen, Vyom Sharma, Wenhao Wang
  • Patent number: 11501739
    Abstract: An operation method for virtually partitioning a display panel includes establishing a plurality of first links between a plurality of transmitter and a receiver, establishing a second link between the receiver and a central controller, acquiring quantity data of the plurality of transmitter by the central controller, generating an operational interface by virtually partitioning the display panel by the central controller according to the quantity data, and controlling the receiver for operating a transmitter to executing at least one operational function by the central controller through the second link and a first link or directly controlling the transmitter to executing the at least one operational function by the central controller through a third link when a virtual key corresponding to the transmitter displayed on the operational interface generated by the central controller is triggered.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 15, 2022
    Assignees: BenQ Intelligent Technology (Shanghai) Co., Ltd, BENQ CORPORATION
    Inventors: Lin-Yuan You, Jung-Kun Tseng, Chia-Nan Shih, Chen-Chi Wu, Chin-Fu Chiang, Chuang-Wei Wu
  • Publication number: 20220359726
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Patent number: 11494150
    Abstract: A dual display regions control method includes establishing a link between a receiver and a first transmitter and a link between the receiver and a second transmitter, transmitting a first image signal to the first transmitter after the first transmitter is triggered, transmitting the first image signal to the receiver, transmitting a second image signal to the second transmitter after the second transmitter is triggered, transmitting the second image signal to the receiver, selecting the first transmitter from the first transmitter and the second transmitter, displaying the first image signal on a first display region through the receiver after the first transmitter is selected, and displaying identification data of the first transmitter and the second transmitter on a second display region through the receiver.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 8, 2022
    Assignees: BenQ Intelligent Technology (Shanghai) Co., Ltd, BENQ CORPORATION
    Inventors: Chen-Chi Wu, Chin-Fu Chiang, Chia-Nan Shih, Lin-Yuan You, Chuang-Wei Wu, Jung-Kun Tseng
  • Patent number: 11496708
    Abstract: A video conference system including a transmitter device and a receiver device is provided. The transmitter device includes a transmitter control unit, a transmitter input interface, a transmitter video circuit and a first wireless transmission module. The transmitter control unit is coupled to a video output port of an information system and receive a first video data from the video output port. The transmitter input interface receives a second video data from a first video source. The transmitter video circuit combines the first video data and the second video data as a combined video data. The first wireless transmission module transmits the combined video data to the receiver device. The receiver device, coupled to the display device, includes a second wireless transmission module, which receives the combined video data. The receiver device transmits the combined video data to the display device.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 8, 2022
    Assignee: BenQ Corporation
    Inventors: Lin-Yuan You, Chen-Chi Wu
  • Patent number: 11495635
    Abstract: An image sensor may include a polydimethylsiloxane (PDMS) layer that is subwavelength, hydrophobic, and/or antireflective. The PDMS layer may be fabricated to include a surface having a plurality of nanostructures (e.g., an array of convex protuberances and/or an array of concave recesses). The nanostructures may be formed through the use of a porous anodic aluminum oxide (AAO) template that uses a plurality of nanopores to form the array of convex protuberances and/or the array of concave recesses. The nanostructures may each have a respective width that is less than the wavelength of incident light that is to be collected by the image sensor to increase light absorption by increasing the angle of incidence for which the image sensor is capable of collecting incident light. This may increase the quantum efficiency of the image sensor and may increase the sensitivity of the image sensor.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ming Lin, Chen-Chi Wu, Chen-Kuei Chung
  • Publication number: 20220344509
    Abstract: A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Wen-Han Fang, Po-Chi Wu
  • Publication number: 20220344215
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 11478321
    Abstract: Indicators for indicating the integrity of a seal of a sterilization container are provided. For example, a seal indicator may indicate whether the container is sufficiently sealed to prevent an ingress of contaminants into the container. If the container is sufficiently sealed, the seal indicator is in one state and displays a first indicium, and if the sterilization container is not sufficiently sealed, the seal indicator is in another state and displays a second indicium. Thus, the seal indicator undergoes a visible change in state when the sterilization container transitions from unsealed to sealed, such that the user may be assured that the container is properly sealed to maintain sterility of the articles post-sterilization. Further, the seal indicator undergoes a visible change in state if the seal is subsequently broken, to signal to the user that the seal and the sterility of the container interior has been compromised.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 25, 2022
    Assignee: O&M Halyard, Inc.
    Inventors: Ruoya Wang, Anthony Stephen Spencer, Kun-Chi Wu, Tracy J. White, Edward B. Madsen, Justin J. Coker, Nathan C. Griffith
  • Publication number: 20220336667
    Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Cheng-Yen YU, Po-Chi WU, Yueh-Chun LAI
  • Publication number: 20220328662
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Bo-Feng Young, Po-Chi Wu, Che-Cheng Chang
  • Publication number: 20220328097
    Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Wei-jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
  • Patent number: 11469145
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chai-Wei Chang, Po-Chi Wu, Wen-Han Fang
  • Patent number: 11468803
    Abstract: A display arrangement includes a base, a decorative shell having a front cover and a back cover, an elongated central post that is rotatably coupled to the decorative shell and fixedly coupled to the base, a light source disposed on the elongated central post and within the shell, such that the light is visible though at least one opening in the shell, a stem coupled to the shell and coupled to the elongated central post, the stem having a magnet on one end, and a coil configured to receive energy from a power source to cause an arcing motion of the magnet, the stem, and thereby the decorative shell. The display arrangement can include a second shell disposed horizontally above the decorative shell and coupled to the decorative shell, and can also include a third shell disposed horizontally below the decorative shell, and that is coupled to the decorative shell.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: October 11, 2022
    Assignee: Fourstar Group Inc.
    Inventor: Yu-Chi Wu
  • Patent number: 11462639
    Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Pan, Chia-Ta Hsieh, Po-Wei Liu, Yun-Chi Wu