Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes the following operations: providing a semiconductor substrate; performing a first cutting operation along a first set of cutting lines of the semiconductor substrate; and performing a second cutting operation along a second set of cutting lines of the semiconductor substrate later than performing the first cutting operation, wherein the second set of cutting lines are arranged interlacedly with the first set of cutting lines along a first direction.

Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Abstract: A seal arrangement is provided for sealing an exposed edge of a composite laminate part having a fay surface configured to be joined to a structure. The seal arrangement includes a precured edge seal covering the exposed edge and a cover covering the edge seal. A seal bead located within a recess in the fay surface of the part forms a seal between the part and the structure.

Abstract: A wireless projecting control method includes setting at least one operation restriction, communicating a transmitter with a receiver or a communication device for executing at least one restricted operation by the transmitter or the receiver, and selectively or restrictedly projecting an image signal to a display device by the receiver after the transmitter or the receiver executes the at least one restricted operation. The image signal is generated by the communication device. The transmitter is used for transmitting the image signal to the receiver according to the at least one operation restriction.

Abstract: A method for expanding functions of a conference system includes providing a first circuit board and a second circuit board disposed in the receiver, receiving a first wireless packet transmitted from the first transmitter merely through a second communication module of the second circuit board, controlling the second communication module for performing an unpacking process of the first wireless packet by a second processor of the second circuit board to generate first compressed media data, generating a first command signal by the second processor of the second circuit board for controlling a first processor of the first circuit board to receive the first compressed media data through a data channel, and decompressing the first compressed media data by the first processor for acquiring first media contents of the first transmitter.

Abstract: The present disclosure provides a method for queuing and a related electronic device. The method for queuing in the present disclosure includes: receiving user data of a user; receiving a current serial number and a quantity of queued people of a service station; determining a queuing time based on the current serial number, the quantity of queued people, and a serial number of the user data; receiving a quantity of waiting people of a first stop in response to a first demand value of the user data being true; determining a first waiting time based on the quantity of waiting people of the first stop; and transmitting a first signal of going to the first stop to the user, and queuing the user in a queue of the service station and a queue of the first stop, in response to the first waiting time being less than the queuing time.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure over a substrate. The method includes forming a dielectric layer over the substrate and the first fin structure. The dielectric layer has a first trench exposing a first portion of the first fin structure. The method includes forming a first work function layer in the first trench. The method includes forming a first mask layer over the first work function layer in the first trench, wherein an upper portion of the first work function layer in the first trench is exposed by the first mask layer. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench.

Abstract: Molecular computer techniques for solving a computational problem using an array of reaction sites, for example, droplets, are disclosed. The problem may be represented as a Hamiltonian in terms of problem variables and problem parameters. The reaction sites may have a physicochemical property mapping to discrete site states corresponding to possible values of the problem variables. In a purely molecular approach, the reaction sites have intra-site and inter-site couplings enforced thereon representing the problem parameters, and the array is allowed to evolve, subjected to the enforced couplings, to a final configuration conveying a solution to the problem. In a hybrid classical-molecular approach, an iterative procedure may be performed that involves feeding read-out site states into a digital computer, determining, based on the problem parameters, perturbations to be applied to the states, and allowing the array to evolve under the perturbations to a final configuration conveying a solution to the problem.

Abstract: Occlusion of facial features may be detected and assessed in an image captured by a camera on a device. Landmark heat maps may be used to estimate the location of landmarks such as the eyes, mouth, and nose of a user's face in the captured image. An occlusion heat map may also be generated for the captured image. The occlusion heat map may include values representing the amount of occlusion in regions of the face. The estimated locations of the eyes, mouth, and nose may be used in combination with the occlusion heat map to assess occlusion scores for the landmarks. The occlusion scores for the landmarks may be used control one or more operations of the device.

Abstract: A level shifter circuit for translating input signal to output signal is disclosed. The level shifter includes an input stage and a latch stage. The latch stage comprises at least a transistor characterized in a substantially matched transconductance with the input stage for preventing a discrete realization of a voltage clamp circuit. The transistor is a semiconductor device including a source region having a source doping region and a drain region having a first doping region and a second doping region. The first doping region is doped with a first conductivity impurity. The second doping region is disposed around the first doping region so as to surround the first doping region, and is doped with a second conductivity impurity. The second doping region has a higher on-resistance than the first doping region, thereby a high resistive series path is created by the second doping region to mimic an embedded resistor.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure which has a first corner. The semiconductor device also includes a first well region with a first conductive type. The semiconductor device includes further includes a gate structure over the first well region and covers a portion of the first corner of the first isolation structure. In addition, the semiconductor device includes a first doped region and a second doped region disposed on two opposites of the gate structure. Each of the first doped region and the second doped region has the first conductive type. The semiconductor device also includes a first counter-doped region in the first well region with a second conductive type different from the first conductive type. The first counter-doped region covers the first corner of the first isolation structure.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A method for forming an integrated circuit structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; forming a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, in which the dielectric layer has a first portion alongside a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode alongside the first portion of the dielectric layer; and forming source/drain features in the semiconductor substrate.