Abstract: A major challenge in the development of anion exchange membranes for fuel cells is the design and synthesis of highly stable (chemically and mechanically) and conducting membranes. Membranes that can endure highly alkaline environments while rapidly transporting hydroxides are desired. A design for using cross-linked polymer membranes is disclosed to produce ionic highways along charge delocalized pyrazolium and homoconjugated triptycenes. The ionic highway membranes show improved performance in key parameters. Specifically, a conductivity of 111.6 mS cm?1 at 80° C. was obtained with a low 7.9% water uptake and 0.91 mmol g?1 ion exchange capacity. In contrast to existing materials, these systems have higher conductivities at reduced hydration and ionic exchange capacities, emphasizing the role of the highway. The membranes retain more than 75% of initial conductivity after 30 days of alkaline stability test.

Abstract: A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: A wireless communications pairing method includes providing a receiver and a first transmitter linked to the receiver, establishing a first link between the first transmitter and a second transmitter, transmitting pairing information from the first transmitter to the second transmitter through the first link, establishing a second link between the second transmitter and the receiver according to the pairing information after the second transmitter receives the pairing information, transmitting an image signal from an image signal source coupled to the second transmitter to the second transmitter after the second transmitter is triggered, processing the image signal by the second transmitter for transmitting the image signal from the second transmitter to the receiver, and controlling a display device for displaying an image by the receiver according to the image signal.

Abstract: A data authorization controlling and matching system includes a receiver, a plurality of display devices, and at least one transmitter. The receiver is used for receiving an image signal. The plurality of display devices are coupled to the receiver for displaying the image signal. The at least one transmitter is coupled to the receiver for outputting the image signal. After a member list saved in the receiver is configured, a data link between the receiver and the at least one transmitter is established. Hardware information of the at least one transmitter is saved in the receiver. The receiver automatically identifies the at least one transmitter according to the hardware information of the at least one transmitter. After the at least one transmitter is identified, the receiver sets authorization information of the at least one transmitter.

Abstract: The present disclosure relates to immunogenic compositions comprising a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) antigen, and a toll-like receptor 9 (TLR9) agonist, such as an oligonucleotide comprising an unmethylated cytidine-phospho-guanosine (CpG) motif. The immunogenic compositions are suitable for stimulating an immune response against a SARS-CoV-2 in an individual in need thereof.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dielectric layer over the substrate, the first fin structure, and the second fin structure. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

Abstract: An image sensor may include a polydimethylsiloxane (PDMS) layer that is subwavelength, hydrophobic, and/or antireflective. The PDMS layer may be fabricated to include a surface having a plurality of nanostructures (e.g., an array of convex protuberances and/or an array of concave recesses). The nanostructures may be formed through the use of a porous anodic aluminum oxide (AAO) template that uses a plurality of nanopores to form the array of convex protuberances and/or the array of concave recesses. The nanostructures may each have a respective width that is less than the wavelength of incident light that is to be collected by the image sensor to increase light absorption by increasing the angle of incidence for which the image sensor is capable of collecting incident light. This may increase the quantum efficiency of the image sensor and may increase the sensitivity of the image sensor.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: The present disclosure is related to a power module. The power module includes first fasteners and power devices. The power devices are adjacently disposed and locked by the first fasteners. Each of the power devices packages a power electronic therein. Each of the power devices includes a first extending portion. The first extending portion extends from a side of the power device. The first extending portion includes at least one first curved opening for receiving the first fastener. The first curved openings are adjacently disposed to form a first inserting hole. The first fastener passes through the first inserting hole.

Abstract: A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.

Abstract: A pump system for pumping a coolant fluid for cooled radiofrequency ablation treatment includes a housing having a front, a back, a right side, a left side, a top surface, and a bottom surface, and a plurality of peristaltic pump assemblies. The top surface of the housing includes a central channel between at least two of the peristaltic pump assemblies configured to drain fluid away from the front of the housing. A cooled radiofrequency ablation system additionally includes a pump system and a generator having mating surfaces such that the pump system can sit stably on top of the generator.

Abstract: Watch bands described herein include electrochromic features that provide adjustable color control based on an applied voltage to offer a variety of colors and color combinations to be displayed by a single band. The user or a control system can control, select, and/or adjust one or more colors of the watch band for visual display. Accordingly, a variety of colors can be displayed at different times without requiring different watch bands for each color or color combination. The color changing features can be used as a visual output of information from the watch to the user.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.

Abstract: An audio processing device includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: An audio dose monitoring circuit includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: An audio processing device includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.