Abstract: Enclosure assemblies with integrating flashing for protecting an accessory on a rooftop. The enclosure assemblies can include a base configured to protect the rooftop from water intrusion and a cover configured to be joined to the raised portion of the base. The base can include a bottom wall and a raised portion extending from the bottom wall. The base can include an uphill portion configured to be positioned beneath at least one full course of roof shingle on the rooftop, without having to cut the roof shingle. The raised portion can be disposed off-center relative to the central transverse axis of the bottom wall, leaving the uphill portion of the bottom wall uncovered.

Abstract: A multi-level switching converter circuit for converting a first voltage to a second voltage or convert the second voltage to the first voltage, includes: a power stage circuit and a control circuit. Through a valley current mode control, the conversion control circuit generates a first ramp signal to determine a first duty ratio of the first control signal, and generates a second ramp signal to determine a second duty ratio of the second control signal, thereby a switching node connected to one end of an inductor is switched between two of k levels of voltages, such that the first voltage or the second voltage is regulated to a predetermined target level, and a flying capacitor voltage across the flying capacitor is regulated and balanced at one (k-1)th of the first voltage.

Abstract: A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes receiving a workpiece having gate structures over channel regions on a substrate and source/drain (S/D) features adjacent to the channel regions. The method then forms tungsten S/D contacts over the S/D features in a first ILD layer by a first selective bottom-up metal growth process. The method forms tungsten S/D vias over the tungsten S/D contacts in a second ILD layer by a second selective bottom-up metal growth process. And after forming the tungsten S/D vias, the method forms tungsten gate vias over the gate structures in the first and the second ILD layer. The forming of the tungsten gate vias includes forming a tungsten seed layer by physical vapor deposition (PVD), and depositing tungsten directly on horizontal and sidewall surfaces of the tungsten seed layer by chemical vapor deposition (CVD).

Abstract: The invention provides a system and a method thereof for establishing an extubation prediction using a machine learning model capable of obtaining an extubation prediction model and key features used by the extubation prediction model through training and/or verification of a machine learning model, and analyzing key feature data of a patient in real time through the extubation prediction model in order to obtain a possibility of extubation of the patient and its related explanation. Accordingly, the system and the method thereof for establishing the extubation prediction using the machine learning model disclosed in the invention are used as a tool for clinical caregivers to evaluate extubation in order to reduce a possibility of reintubation due to inability to breathe spontaneously after extubation.

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Abstract: A contact lens includes a first optical region, a second optical region, and a transition region. The first optical region is shaped to form a first power profile. The second optical region is shaped to form a second power profile. The transition region is joined between the first optical region and the second optical region and is shaped to form a third power profile with a power variation radially changing from the first power profile to the second power profile as a radius increasing. The transition region includes a first subzone, a second subzone and a third subzone. Each of the first subzone and the third subzone has a gradual power variation measured from a lens center to a lens edge as compared to the second subzone, and the second subzone has a steep power variation measured from the lens center to the lens edge.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit containing a transistor, a sidewall spacer, a semiconductor region with multiple doped layers, an insulator layer, and a metal layer. The transistor having a channel region, an insulating layer surrounding three sides of the channel region, and a conductive layer surrounding three sides of the channel region. The semiconductor region has an outer sidewall facing a side of the sidewall spacer opposite from the transistor. The insulator layer surrounds three sides of the semiconductor region. The metal layer surrounds three sides of the insulator layer. The semiconductor region has a width equal to a width of the channel region the transistor along a first line, and the semiconductor region has a second width less than a second width of the channel region of the transistor along a second line.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The nozzle lips at the two sides of the slot die coating apparatus are extended to close the substrate to prevent to hit the obstacle of the substrate during coating. Also, the height for coating of the slot die coating apparatus is controllable to achieve the optimized coating.

Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The height for coating of the slot die coating apparatus is adjustable, and the slurry may be exposed from the first flow path or the second flow path. Therefore, hitting the obstacle of the substrate can be avoided during coating to achieve the optimized coating.

Abstract: Provided is a method for preparing a tissue section, including treating a tissue specimen with a clearing agent and at least one labeling agent to obtain a cleared and labeled tissue specimen; generating a three-dimensional (3D) image of the cleared and labeled tissue specimen; performing an image slicing procedure on the 3D image to generate a plurality of two-dimensional (2D) images; identifying a target 2D image among the plurality of 2D images to obtain a distance value of D1, which indicates the distance between the target 2D image and a predetermined surface of the 3D image; preparing a hardened tissue specimen from the cleared and labeled tissue specimen; and cutting the hardened tissue specimen near a predetermined site to obtain a tissue section, wherein the distance between the predetermined site and a surface of the hardened tissue specimen corresponding to the predetermined surface of the 3D image is D1.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.

Abstract: A method includes: determining whether a first pellicle is to be inspected for inner particles; and in response to the first pellicle being to be inspected: forming a mask layer on a substrate; forming a defocused light path by shifting a mask assembly; exposing the mask layer by defocused light having a focal plane separated from the first pellicle by a distance; taking an image of the substrate; determining whether a threshold value is exceeded by analyzing the image; in response to the threshold value being exceeded, replacing the first pellicle with a second pellicle; and in response to the threshold value not being exceeded, processing production wafers using the first pellicle.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant includes: a first portion, on the second die; a second portion, sandwiched between a first sidewall of the first die and a first sidewall of the second die; and a third portion, covering a second sidewall of the second die. The second encapsulant, laterally encapsulating the first die, the second die and the first encapsulant. The conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The third portion of first encapsulant is sandwiched between the second sidewall of the second die and the second encapsulant.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Abstract: A semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of a semiconductor substrate, a second three-dimensional semiconductor structure of a second conductivity type also protruding from the surface of the semiconductor substrate, and a first transistor. The first transistor includes a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, and a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure.