Patents by Inventor Chi Yang
Chi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250144618Abstract: The present disclosure provides a biochemical test module. The biochemical test module includes a first reaction piece and a second reaction piece. The first reaction piece includes a first substrate; a first separator located on the first substrate and having a first flow channel exposing at least a portion of the first substrate; and a first cover covering the first separator. The first hole is connected with a first channel. The first reaction piece has a perforated structure penetrating the first cover, the first separator and the first substrate. The second reaction piece is disposed on one side of the first reaction piece adjacent to the first substrate and includes a second substrate; a second separator located on the second substrate and having a second flow channel exposing at least a portion of the second substrate; and a second cover covering the second separator and joined to the first substrate.Type: ApplicationFiled: January 5, 2024Publication date: May 8, 2025Inventors: YI-SHENG LIN, CHI-YANG PENG, NAI-JUI CHUEH, CHENG-CHE WEN, TANG-CHING KUAN
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Patent number: 12292687Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.Type: GrantFiled: July 25, 2023Date of Patent: May 6, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi Yang, Tsung-Hsun Lee, Jian-Yuan Su, Ching-Juinn Huang, Po-Chung Cheng
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Publication number: 20250141452Abstract: An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.Type: ApplicationFiled: December 8, 2023Publication date: May 1, 2025Applicant: Macronix International Co., Ltd.Inventors: Chun-Hao Tsai, Shang-Chi Yang, Shiang-Yuan Li, Hsuan-Chieh Lin
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Publication number: 20250134891Abstract: The present disclosure relates to combinations of inhibitors of SOS1 and inhibitors of mTOR useful in the treatment of diseases or disorders.Type: ApplicationFiled: May 11, 2022Publication date: May 1, 2025Inventors: Bianca Jennifer LEE, Grace J. LEE, David Church MONTGOMERY, Elsa QUINTANA, Mallika SINGH, Jacqueline SMITH, David E. WILDES, Yu Chi YANG
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Publication number: 20250133761Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.Type: ApplicationFiled: December 30, 2024Publication date: April 24, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
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Patent number: 12278124Abstract: A load lock in which the pumping speed is controlled so as to minimize the possibility of condensation is disclosed. The load lock is in communication with a vacuum pump and a valve. A controller is used to control the valve such that the supersaturation ratio within the load lock does not exceed a predetermined threshold, which is less than or equal to the critical value at which vapor condenses. In certain embodiments, a computer model is used to generate a profile, which may be a pumping speed profile or a pressure profile, and the valve is controlled according to the profile. In another embodiment, the load lock comprises a temperature sensor and a pressure sensor. The controller may calculate the supersaturation ratio based on these parameters and control the valve accordingly.Type: GrantFiled: October 28, 2021Date of Patent: April 15, 2025Assignee: Applied Materials, Inc.Inventors: D. Jeffrey Lischer, Bon-Woong Koo, Dawei Sun, Chi-Yang Cheng, Paul Joseph Murphy, Frank Sinclair, Gregory Edward Stratoti, Tseh-Jen Hsieh, Wayne Chen, Guy Oteri
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Publication number: 20250116938Abstract: A method includes: forming a mask layer on a semiconductor wafer; forming a tin droplet, including: supplying tin to a high-pressure reservoir from a low-pressure reservoir; monitoring a level of tin in the high-pressure reservoir by at least two electrodes attached to the high-pressure reservoir; in response to the level of the tin exceeding a threshold value, supplying the tin to a droplet generator from the high-pressure reservoir; forming the tin droplet by the droplet generator using the tin supplied from the high-pressure reservoir; generating light by the tin droplet; and patterning the mask layer by the light.Type: ApplicationFiled: October 9, 2023Publication date: April 10, 2025Inventors: Chi YANG, Po-Yuan YEH, Che-Hsin LIN, Jen Chieh YU, Chung Wen LUO
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Publication number: 20250114364Abstract: The present disclosure relates to methods for the treatment of diseases or disorders (e.g., cancer) with mTOR inhibitors. Specifically, the disclosure relates to methods of treating a subject having a cancer by administering a particular dosage of an mTOR inhibitor. In some embodiments this disclosure includes methods for delaying, preventing, or treating acquired resistance to RAS inhibitors using a dosage of an mTOR inhibitor. In some embodiments, this disclosure relates to methods of treating or preventing adverse events associated with administration of an mTOR inhibitor using tacrolimus.Type: ApplicationFiled: September 16, 2024Publication date: April 10, 2025Inventors: Bojena BITMAN, W. Clay GUSTAFSON, Ed LORENZANA, Justin G. MEYEROWITZ, Yu Chi YANG, Mallika SINGH, Zhengping WANG, Zhican WANG
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Publication number: 20250105789Abstract: A differential amplifier includes an input pair of transistors with a source-side resistor circuit, having a transistor biased in a triode region, and a current source. The resistor circuit in combination with a capacitance, causes source degeneration in the amplifier. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit biases the first MOS transistor and the second MOS transistor in a triode region. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.Type: ApplicationFiled: September 21, 2023Publication date: March 27, 2025Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shang-Chi YANG, Tung-Yu LI, Jian-Syu LIN
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Publication number: 20250106974Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih LAI, Han-Lung CHANG, Chi YANG, Shang-Chieh CHIEN, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG
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Publication number: 20250100986Abstract: Compounds having a structure of Formula I: or a pharmaceutically acceptable salt, tautomer or stereoisomer thereof, wherein R1, R2, R3, R11a, R11b, R11c, R11d, and X, are as defined herein, are provided. Uses of such compounds for modulating androgen receptor activity, imaging diagnostics in cancer and therapeutics, and methods for treatment of subjects in need thereof, including prostate cancer are also provided.Type: ApplicationFiled: October 17, 2024Publication date: March 27, 2025Inventors: Raymond John ANDERSEN, Marianne Dorothy SADAR, Kunzhong JIAN, Nasrin R. MAWJI, Jun WANG, Carmen Adriana BANUELOS, Yu-Chi YANG
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Publication number: 20250102580Abstract: A calibration system and a calibration method for state of charge (SOC) and state of health (SOH) in an energy storage system are provided. The calibration system includes a Main Battery Management System (MBMS) and a plurality of racks, wherein, when the MBMS determines that one of the plurality of racks meets auto-calibration conditions, the MBMS utilizes a battery feature value extraction algorithm to obtain feature value data of each of battery packs, and predicts the number of battery cycles for each of the battery packs via a battery aging correction model. In this way, the SOC and the SOH for each of the battery packs can be accurately calculated, so that maintenance personnel can clearly comprehend the status of each of the racks, thereby improving the efficiency of power management.Type: ApplicationFiled: January 22, 2024Publication date: March 27, 2025Applicant: SIMPLO TECHNOLOGY CO., LTD.Inventors: Ya-Mei CHANG, Chi-Yang CHENG, Chun-Chang CHEN, Chia-Wei CHEN
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Patent number: 12261358Abstract: An antenna device includes a casing, a circuit board, and an antenna. The casing has a positioning structure. The circuit board is disposed in the casing. The antenna is disposed in the casing and includes a main body portion and a connection portion connected to each other. The connection portion is connected to a surface of the circuit board. The main body portion is extended on a plane defined by a first axial direction and a second axial direction. The first axial direction is perpendicular to the surface and the second axial direction is parallel to the surface. The main body portion is positioned on the positioning structure and separated from the circuit board.Type: GrantFiled: March 19, 2024Date of Patent: March 25, 2025Assignee: Chicony Electronics Co., Ltd.Inventors: Chi-Yang Chiu, Jung-Hsiu Lee, Yen-Ching Lee
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Patent number: 12261203Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.Type: GrantFiled: January 19, 2022Date of Patent: March 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chih Lin, Yun-Ju Pan, Szu-Chi Yang, Jhih-Yang Yan, Shih-Hao Lin, Chung-Shu Wu, Te-An Yu, Shih-Chiang Chen
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Patent number: 12245801Abstract: Disclosed is an adjustable cryoablation needle, comprising a needle rod (3), a front-segment heat-insulated tube (1), a rear-segment heat-insulated tube (2), and an gas inlet structure (7) penetrating the needle rod (3) and the front-segment heat-insulated tube (1), wherein the needle rod (3) can move relative to the rear-segment heat-insulated tube (2) in the axial direction of the rear-segment heat-insulated tube (2) so as to adjust a first axial distance between the front end of the rear-segment heat-insulated tube (2) and the front end of the needle rod (3); and the front-segment heat-insulated tube (1) can move relative to the rear-segment heat-insulated tube (2) in the axial direction of the rear-segment heat-insulated tube (2). The adjustable cryoablation needle can prevent the inconvenience caused by a doctor selecting the model of the cryoablation needle.Type: GrantFiled: June 17, 2020Date of Patent: March 11, 2025Assignee: ACCU TARGET MEDIPHARMA (SHANGHAI) CO., LTD.Inventors: Chi Yang, Binkai Xu, Yinlong Wu, Zhaohua Chang
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Publication number: 20250070075Abstract: A package structure includes a wiring structure, a first electronic device and a reinforcement structure. The first electronic device is disposed over the top surface of the wiring structure, and has a bottom surface facing the top surface of the wiring structure. The first electronic device includes a plurality of first wires. The reinforcement structure is disposed over the top surface of the wiring structure, and includes a plurality of second wires directly contacting the plurality of first wires to reduce a variation of an elevation of the bottom surface of the first electronic device with respect to the top surface of the wiring structure.Type: ApplicationFiled: August 24, 2023Publication date: February 27, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Yang CHIANG, Man-Wen TSENG, Chien-Ching CHEN
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Patent number: 12235594Abstract: A method for performing a lithography process is provided. The method includes forming a photoresist layer over a substrate, providing a plurality of target droplets to a source vessel, and providing a plurality of first laser pulses according to a control signal provided by a controller to irradiate the target droplets in the source vessel to generate plasma as an EUV radiation. The plasma is generated when the control signal indicates a temperature of the source vessel is within a temperature threshold value. The method further includes directing the EUV radiation from the source vessel to the photoresist layer to form a patterned photoresist layer and developing and etching the patterned photoresist layer to form a circuit layout.Type: GrantFiled: May 31, 2023Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi Yang, Ssu-Yu Chen, Shang-Chieh Chien, Chieh Hsieh, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
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Publication number: 20250062184Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 12230589Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: GrantFiled: May 30, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
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Publication number: 20250049810Abstract: The disclosure features methods of treating RAS disorders using Compound A, or a pharmaceutically acceptable salt thereof. The disclosure also features methods of treating RAS disorders (e.g., cancer) including combinations of Compound A, or a pharmaceutically acceptable salt thereof, and additional therapeutic agent.Type: ApplicationFiled: August 6, 2024Publication date: February 13, 2025Inventors: Jingjing JIANG, Mallika SINGH, Zhengping WANG, Zhican WANG, Yu Chi YANG, Lei BAO, Richa DUA