Abstract: The present disclosure relates to a compound of Formula I, or a geometric isomer, enantiomer, diastereomer, racemate, atropisomer, pharmaceutically acceptable salt, prodrug or solvate thereof. The present disclosure further relates to a composition comprising the compound of Formula (I). The compound and the composition described herein can be used to inhibit NADPH oxidase activity.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: An electronic device having a detachable memory is provided with a docking connector, and includes a device body and a memory. The device body has an accommodating slot and a stopping portion provided corresponding to the accommodating slot, and the stopping portion and the accommodating slot jointly form a displacement space in between. The memory is provided with a connector and a protruding stopped portion. When the memory is accommodated in the accommodating slot, the stopped portion is moved along into the displacement space and is stopped by the stopping portion, and the connector is docked with the docking connector. Thus, the memory is provided with an anti-misplugging effect.

Abstract: The invention provides method and associated controller for improving temperature adaptability of an amplifier; the method may include: receiving a temperature value, and adjusting a supply voltage supplied to the amplifier according to the temperature value.

Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing reference voltages, e.g., with current compensation, in memory systems, e.g., non-volatile memory systems. In one aspect, an integrated circuit includes: an operational amplifier configured to receive input voltages and a supply voltage and output a control voltage based on the input voltages and the supply voltage; an output circuitry configured to receive the control voltage from the operational amplifier and the supply voltage, provide the input voltages to the operational amplifier, and output a reference voltage; and a compensation circuitry coupled to the output circuitry and configured to output a compensation current to compensate the output circuitry such that the reference voltage is substantially constant. The output circuitry is configured to generate the reference voltage based on the control voltage and the compensation current.

Abstract: A system for controlling plasma position in extreme ultraviolet lithography light sources may include a vacuum chamber, a droplet generator to dispense a stream of droplets into the vacuum chamber, wherein the droplets are formed from a metal material, a laser light source to fire a plurality of laser pulses, including at least a first pulse and a second pulse, into the vacuum chamber, a sensor to detect an observed plasma position within the chamber, wherein the observed plasma position comprises a position at which the plurality of laser pulses vaporizes a droplet of the stream of droplets to produce a plasma that emits extreme ultraviolet radiation, and a first feedback loop connecting the sensor to the laser light source, wherein the first feedback loop adjusts a time delay between the first and second pulses to minimize a difference between the observed plasma position and a target plasma position.

Abstract: A load lock in which the pumping speed is controlled so as to minimize the possibility of condensation is disclosed. The load lock is in communication with a vacuum pump and a valve. A controller is used to control the valve such that the supersaturation ratio within the load lock does not exceed a predetermined threshold, which is less than or equal to the critical value at which vapor condenses. In certain embodiments, a computer model is used to generate a profile, which may be a pumping speed profile or a pressure profile, and the valve is controlled according to the profile. In another embodiment, the load lock comprises a temperature sensor and a pressure sensor. The controller may calculate the supersaturation ratio based on these parameters and control the valve accordingly.

Abstract: In an embodiment, a method includes: heating a byproduct transport ring of an extreme ultraviolet source, the byproduct transport ring disposed beneath vanes of the extreme ultraviolet source; after heating the byproduct transport ring for a first duration, heating the vanes; after heating the vanes, cooling the vanes; and after cooling the vanes for a second duration, cooling the byproduct transport ring.

Abstract: A method for manufacturing epitaxial films with multiple stress states, comprising steps of: providing a first single crystal substrate, and forming a sacrificial layer and a first epitaxial film on the first single crystal substrate, wherein the first epitaxial film is made of a first material; removing the sacrificial layer to separate the first epitaxial film from the first single crystal substrate; transferring the first epitaxial film to a second single crystal substrate, wherein the second single crystal substrate is made of a second material, a partial surface of the second single crystal substrate being overlapped by the first epitaxial film; applying epitaxies onto the first epitaxial film and the second single crystal substrate to form a second epitaxial film on the first epitaxial film and the second single crystal substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A motor commutation waveform generating circuit is provided. The motor commutation waveform generating circuit includes: an edge detection circuit, configured to receive sensing signals of the motor and derive a clock signal indicating a commutation switching point of the motor; an angle cutting circuit, controlled by the clock signal to generate an angle indication pulse indicating a rotation angle of the motor; a synthetic wave generating circuit, using the angle indication pulse to sequentially change waveform voltages corresponding to required angles and output them in segments; and a signal combining circuit, controlled by the clock signal to combine waveform voltage signals generated by the synthetic wave generating circuit, thereby obtaining a plurality of synthetic waveforms provided to a drive control system of the motor for drive control after pulse width modulation.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: A motor commutation waveform generating circuit is provided. The motor commutation waveform generating circuit includes: an edge detection circuit, configured to receive sensing signals of the motor and derive a clock signal indicating a commutation switching point of the motor; an angle cutting circuit, controlled by the clock signal to generate an angle indication pulse indicating a rotation angle of the motor; a synthetic wave generating circuit, using the angle indication pulse to sequentially change waveform voltages corresponding to required angles and output them in segments; and a signal combining circuit, controlled by the clock signal to combine waveform voltage signals generated by the synthetic wave generating circuit, thereby obtaining a plurality of synthetic waveforms provided to a drive control system of the motor for drive control after pulse width modulation.

Abstract: A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.

Abstract: A surgical pad can comprise a flexible pad portion configured to be positioned over an opening in a target tissue. A plurality of elongate ribs can be distributed across a surface of the flexible pad portion oriented away from the target tissue and can be coupled to the flexible pad portion. A surgical pad can comprise a central opening configured to be aligned with an opening in a target tissue, and a plurality of edge openings distributed around an outer edge portion. A method can comprise positioning a spacer between a target tissue and a surgical pad to adjust the tension of surgical cords secured to surgical pad. A method can comprise positioning a spacer between a surface of a surgical pad oriented away from a target tissue and portions of surgical cords secured over the surface of the surgical pad, to adjust the tension of the surgical cords.

Abstract: An antenna device includes a casing, a circuit board, and an antenna. The casing has a positioning structure. The circuit board is disposed in the casing. The antenna is disposed in the casing and includes a main body portion and a connection portion connected to each other. The connection portion is connected to a surface of the circuit board. The main body portion is extended on a plane defined by a first axial direction and a second axial direction. The first axial direction is perpendicular to the surface and the second axial direction is parallel to the surface. The main body portion is positioned on the positioning structure and separated from the circuit board.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: The present invention relates to a container. More specifically, it relates to a container having a lower portion with a bottom and a plurality of walls defining an interior space. The container also includes a cover attached to one of the walls via a hinge and configured to move between a closed position and a fully open position, wherein in said closed position, access to the interior space is prohibited, and in said fully open position, access to the interior space is permitted and the cover is at an angle (?) of greater than or equal to 90 degrees with respect to the lower portion.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.