Patents by Inventor Chi-Yang Yu
Chi-Yang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200328173Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 10804245Abstract: A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.Type: GrantFiled: January 5, 2018Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang
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Patent number: 10790210Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.Type: GrantFiled: October 25, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chien-Hsun Lee, Yu-Min Liang
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Patent number: 10777467Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.Type: GrantFiled: November 4, 2019Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
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Publication number: 20200279790Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 14, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20200219788Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.Type: ApplicationFiled: March 17, 2020Publication date: July 9, 2020Inventors: CHIN-LIANG CHEN, CHI-YANG YU, KUAN-LIN HO, YU-MIN LIANG
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Patent number: 10700031Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars.Type: GrantFiled: December 11, 2018Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 10658263Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: May 31, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 10622278Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.Type: GrantFiled: April 10, 2019Date of Patent: April 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Liang Chen, Chi-Yang Yu, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20200066598Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
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Publication number: 20200043819Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.Type: ApplicationFiled: October 25, 2018Publication date: February 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chien-Hsun Lee, Yu-Min Liang
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Publication number: 20200006171Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Hai-Ming Chen, Yu-Min Liang, Jung Wei Cheng, Chien-Hsun Lee
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Patent number: 10522436Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.Type: GrantFiled: February 28, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yang Yu, Hai-Ming Chen, Yu-Min Liang, Jung Wei Cheng, Chien-Hsun Lee
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Publication number: 20190371699Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 10468307Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.Type: GrantFiled: September 18, 2017Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
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Publication number: 20190237385Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: CHIN-LIANG CHEN, CHI-YANG YU, KUAN-LIN HO, YU-MIN LIANG
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Publication number: 20190148250Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.Type: ApplicationFiled: February 28, 2018Publication date: May 16, 2019Inventors: Chi-Yang Yu, Hai-Ming Chen, Yu-Min Liang, Jung Wei Cheng, Chien-Hsun Lee
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Publication number: 20190148340Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.Type: ApplicationFiled: December 8, 2017Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Chien-Hsun Lee, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20190131262Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars.Type: ApplicationFiled: December 11, 2018Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 10276508Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.Type: GrantFiled: September 28, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Chi-Yang Yu, Yu-Min Liang