Abstract: A waveguide photodetector includes a slab over a substrate, first and second contact portions protruding upward from the slab, and a ridge protruding upward from the slab between the first and second contact portions. A first semiconductor layer is over the substrate and includes a first doped region in the first contact portion, a second doped region in the slab between the first contact portion and the ridge, a third doped region and a sixth doped region in the ridge, a fourth doped region in the second contact portion, a fifth doped region in the slab between the second contact portion and the ridge, a first intrinsic region between the sixth and third doped regions, and a second intrinsic region between the sixth and fifth doped regions. A second semiconductor layer is over the first intrinsic region and between the sixth and third doped regions.

Abstract: A semiconductor photonics device includes a plurality of grating couplers, each configured to couple a particular wavelength (or wavelength range) of an optical signal to a waveguide of the semiconductor photonics device. In some implementations, various implementations of optical signal splitters or filters described herein enable respective wavelengths (or respective wavelength ranges) to be passed to each of the grating couplers (while filtering out other wavelengths or other wavelength ranges), thereby enabling the grating couplers to each handle a respective wavelength (or respective wavelength range). This enables multiple wavelengths (or multiple wavelength ranges) to be distributed across multiple grating couplers, which may increase the bandwidth of the semiconductor photonics device relative to a semiconductor photonics device that includes only a single grating coupler.

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure that includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a first electrode and a second electrode stacked over the substrate. A dielectric layer is arranged between the first electrode and the second electrode. A getter layer is disposed over the substrate and is separated from the dielectric layer by the first electrode. The MIM device includes a middle portion having a first non-zero concentration of hydrogen and a peripheral portion having both a second non-zero concentration of hydrogen that is greater than the first non-zero concentration and a third non-zero concentration of hydrogen that is less than the first non-zero concentration. The middle portion includes the dielectric layer and the peripheral portion includes the getter layer.

Abstract: A modulator heater structure may include a plurality of regions having different thicknesses. For example, a heater ring of the modulator heater structure may have a first thickness. A heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. The lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. The greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.

Abstract: Resistors and method of forming the same are provided. A device structure according to the present disclosure includes a substrate, a first intermetal dielectric (IMD) layer over the substrate, a resistor that includes a first resistor layer over the first IMD layer, a second resistor layer over the first resistor layer, and a third resistor layer over the second resistor layer, a second IMD layer over the first IMD layer and the resistor, a first contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer, and a second contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer.

Abstract: Some implementations described herein provide an optical receiver system. The optical receiver system includes optical circuitry that may include a phase shifter device, a demultiplexer device, a power combiner device, and/or a power splitter device. Different combinations of such devices within the optical circuitry may balance and/or reduce photocurrents within the photodiode device to improve a performance (e.g., a bandwidth) of the optical receiver system relative to another optical receiver system that does not include the optical circuitry.

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

Abstract: An optical modulator structure in a photonic integrated circuit includes an L-shaped P-N junction at an optical mode of the optical modulator structure (e.g., an area of the optical modulator structure in which light is generated). The L-shaped P-N junction provides increased area of overlap of the P-N junction at the optical mode relative to another type of junction, such as a horizontal junction or I-shaped junction. The increased area of overlap may enable the optical modulator structure to achieve a greater modulation efficiency.

Abstract: A semiconductor structure includes a substrate, a piezoelectric layer, and a stress structure. The substrate includes a first surface and a second surface, wherein a portion of the substrate proximal to the first surface defines a diaphragm. The piezoelectric layer is disposed over the first surface of the substrate and surrounds the diaphragm, wherein the piezoelectric layer includes a first portion and a second portion arranged along a periphery of the diaphragm from a top view. The stress structure includes a plurality of dielectric layers disposed over the piezoelectric layer and between the substrate and the piezoelectric layer, and a total thickness of a first portion of the stress structure overlapping the first portion of the piezoelectric layer is different from a total thickness of a second portion of the stress structure overlapping the second portion of the piezoelectric layer. A method for manufacturing a semiconductor structure is also provided.

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure and a second conductive structure. A dielectric structure is arranged between the first conductive structure and the second conductive structure. The dielectric structure comprises an upper region over a lower region. The lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region. A passivation layer overlies the second conductive structure and the dielectric structure. The passivation layer comprises a lateral segment contacting the first lateral surface. A height of the lateral segment is greater than a height of the upper region. A top surface of the lateral segment is below a top surface of the passivation layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

Abstract: A method of wavelength tuning in a silicon photonics circuit includes receiving a bus waveguide, a ring resonator optically coupled to the bus waveguide, and a dielectric layer over the bus waveguide and over the ring resonator. The method further includes performing a first heat process at a first temperature to heat up the dielectric layer, where the first heat process shifts an initial resonance wavelength of the ring resonator to a first resonance wavelength shorter than the initial resonance wavelength. The first heat process permanently shifts the initial resonance wavelength to the first resonance wavelength, the first resonance wavelength being a wavelength when no heat is being applied to the ring resonator.

Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.