Abstract: The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.

Abstract: One of the broader forms of the present disclosure involves a method of enhanced defect inspection. The method includes providing a substrate having defect particles and providing a fluid over the substrate and the defect particles, the fluid having a refractive index greater than air. The method further includes exposing the substrate and the defect particles to incident radiation through the fluid, and detecting, through the fluid, radiation reflected or scattered by the defect particles.

Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Abstract: Methods and systems for improving the sensitivity of a variety of conductivity sensing devices, in particular capacitively-coupled contactless conductivity detectors. A parallel inductor is added to the conductivity sensor. The sensor with the parallel inductor is operated at a resonant frequency of the equivalent circuit model. At the resonant frequency, parasitic capacitances that are either in series or in parallel with the conductance (and possibly a series resistance) is substantially removed from the equivalent circuit, leaving a purely resistive impedance. An appreciably higher sensor sensitivity results. Experimental verification shows that sensitivity improvements of the order of 10,000-fold are possible. Examples of detecting particulates with high precision by application of the apparatus and methods of operation are described.

Abstract: An apparatus for liquid chromatography comprises a liquid chromatography separation column on a substrate, wherein the separation column is coupled to a heater on the substrate. A chip-based temperature controlled liquid chromatography device comprises a substrate, a thermal isolation zone, and a separation column thermally isolated from the substrate by the thermal isolation zone. An apparatus for chip-based liquid chromatography comprising a cooling device is provided. A temperature gradient liquid chromatography system comprises a chip-based temperature controlled liquid chromatography device, a fluidic coupling, and an electrical interface. Methods of making and methods of using of chip-based temperature gradient liquid chromatography devices are also provided.

Abstract: Methods and systems for improving the sensitivity of a variety of conductivity sensing devices, in particular capacitively-coupled contactless conductivity detectors. A parallel inductor is added to the conductivity sensor. The sensor with the parallel inductor is operated at a resonant frequency of the equivalent circuit model. At the resonant frequency, parasitic capacitances that are either in series or in parallel with the conductance (and possibly a series resistance) is substantially removed from the equivalent circuit, leaving a purely resistive impedance. An appreciably higher sensor sensitivity results. Experimental verification shows that sensitivity improvements of the order of 10,000-fold are possible. Examples of detecting particulates with high precision by application of the apparatus and methods of operation are described.

Abstract: Systems and methods for monitoring analytes in real time using integrated chromatography systems and devices. Integrated microfluidic liquid chromatography devices and systems include multiple separation columns integrated into a single substrate. Using such a device, parallel analysis of multiple samples can be performed simultaneously and/or sequential analysis of a single sample can be performed simultaneously on a single chip or substrate. The devices and systems are well suited for use in high pressure liquid chromatography (HPLC) applications. HPLC chips and devices including embedded parylene channels can be fabricated using a single mask process.

Abstract: A method for processing nanoparticles using a self assembly mechanism. The method includes flowing a first reactant species through a first channel region, which has a predetermined dimension including a first width and a first depth. The method includes flowing a second reactant species through a second channel region, which also has a predetermined dimension including a second width and a second depth. The method includes outputting the first reactant species through a first orifice exiting the first channel region and outputting the second reactant species through a second orifice exiting the second channel region. Additionally, the method forms an interface region along a first predetermined length in a third channel, which couples the first orifice to the second orifice at the interface region.

Abstract: An apparatus for liquid chromatography comprises a liquid chromatography separation column on a substrate, wherein the separation column is coupled to a heater on the substrate. A chip-based temperature controlled liquid chromatography device comprises a substrate, a thermal isolation zone, and a separation column thermally isolated from the substrate by the thermal isolation zone. An apparatus for chip-based liquid chromatography comprising a cooling device is provided. A temperature gradient liquid chromatography system comprises a chip-based temperature controlled liquid chromatography device, a fluidic coupling, and an electrical interface. Methods of making and methods of using of chip-based temperature gradient liquid chromatography devices are also provided.