Patents by Inventor Chia-Cheng Liu

Chia-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453932
    Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Chyi Liu, Chang-Ming Wu, Shih-Chang Liu, Wei Cheng Wu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
  • Publication number: 20190306990
    Abstract: A display device is provided. The display device includes a display panel, a flexible circuit board, an integrated circuit, and a conductive layer. The flexible circuit board is electrically connected with the display panel and includes a plurality of conductive wires. The integrated circuit is disposed on the flexible circuit board and has a plurality of bumps. The conductive layer is disposed between the integrated circuit and the flexible circuit board and covers a periphery of the integrated circuit. In addition, the conductive layer includes an adhesive and a plurality of conductive particles distributed in the adhesive. Moreover, the bumps are electrically connected with the conductive wires through the conductive particles.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: Innolux Corporation
    Inventors: Wei-Cheng Chu, Chia-Cheng Liu, Chih-Yuan Lee, Chin-Lung Ting, Tong-Jung Wang
  • Publication number: 20190304864
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng
  • Publication number: 20190288068
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 10418290
    Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Hon-Huei Liu, Chia-Hung Lin, Yu-Cheng Tung
  • Patent number: 10418460
    Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
  • Publication number: 20190280502
    Abstract: A charger management method to be implemented by a server includes steps of: with respect to each charger, in response to receipt from the charger in a non-charging state of a notification including a charger identifier (ID) of the charger, updating the state flag of one of charger information sets stored in the server and including the charger ID to a second value; and in response to receipt of a query including a target location from a user end electronic device, selecting, based on the charger information sets and the target location, at least one candidate charging station information set from multiple charging station information sets.
    Type: Application
    Filed: February 25, 2019
    Publication date: September 12, 2019
    Inventors: Ping-Jui HSIEH, Chia-Cheng TU, Te-Chuan LIU, Jen-Chiun LIN, Yuh-Rey CHEN, Po-Yu CHUANG
  • Publication number: 20190278352
    Abstract: A system for managing power supply devices includes a server including a database and a server end processing module. The server end processing module is configured to receive an alteration request from a user end electronic device and an alteration-confirmation signal from a service end electronic device, and send a confirmation response to the service end electronic device based on the received alteration request and alteration-confirmation signal in order for the service end electronic device to enable a target power supply device to update data stored therein.
    Type: Application
    Filed: February 27, 2019
    Publication date: September 12, 2019
    Applicant: KWANG YANG MOTOR CO., LTD.
    Inventors: Chen-Sheng Lin, Chia-Cheng Tu, Jen-Chiun Lin, Po-Yu Chuang, Yuh-Rey Chen, Te-Chuan Liu
  • Publication number: 20190236326
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Publication number: 20190227256
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a carrier, a base, and a first driving assembly. The carrier holds an optical element with an optical axis. The carrier is movably connected to the base. The first driving assembly drives the carrier to move relative to the base. The first driving assembly includes a driving coil disposed on the carrier, and the direction of the winding axis of the driving coil is different from the direction of the optical axis. The carrier has an abutting surface, which faces and is in direct contact with the driving coil. The maximum size of the abutting surface is greater than the maximum size of the driving coil in the direction of the optical axis.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Chi KUO, Chia-Hsiu LIU, Yen-Cheng CHEN, Shao-Chung CHANG, Sin-Jhong SONG
  • Publication number: 20190227337
    Abstract: An optical driving mechanism is provided, including a movable portion, a bottom plate and a biasing assembly. The movable portion is configured to sustain an optical element having an optical axis. The bottom plate has a moving member. The biasing assembly has at least one biasing element for driving the movable portion to move relative to the bottom plate. The bottom plate defines a first electrical connection portion and a second electrical connection portion, and the biasing element is connected to the first and second electrical connection portions. The first electrical connection portion has a fixed body, an insulating layer and a conductive layer, which are sequentially overlapped along the optical axis. The conductive layer is directly and electrically connected to the biasing element. When viewed along the optical axis, the insulating layer protrudes from the fixed body and the conductive layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Chi KUO, Chia-Hsiu LIU, Yen-Cheng CHEN, Shao-Chung CHANG, Sin-Jhong SONG
  • Patent number: 10361295
    Abstract: A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 23, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Patent number: 10347762
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Patent number: 10347720
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20190174084
    Abstract: An image sensor including a first pixel circuit, a second pixel circuit, a first readout line, a second readout line, a first readout circuit, a second readout circuit and an average switch is provided. The first and second pixel circuits are in two columns of a pixel array. The first readout line transmits pixel data of the first pixel circuit to the first readout circuit. The second readout line transmits pixel data of the second pixel circuit to the second readout circuit. The average switch is arranged between the first and second readout lines and used to electrically connect the first and second readout lines in an average mode to average the pixel data on the first and second readout lines.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Chia-Chi KUO, Jui-Te CHIU, Han-Chi LIU, Peng-Sheng CHEN, Yi-Cheng CHIU
  • Publication number: 20190165177
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHING, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Publication number: 20190157456
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.
    Type: Application
    Filed: July 18, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng CHEN, Su-Hao LIU, Kuo-Ju CHEN, Liang-Yin CHEN
  • Publication number: 20190148320
    Abstract: A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 ?m and less than or equal to 14 ?m. In addition, the disclosure further provides an electronic device including the first electronic element.
    Type: Application
    Filed: October 1, 2018
    Publication date: May 16, 2019
    Inventors: Wei-Cheng CHU, Ming-Fu JIANG, Chia-Cheng LIU, Tong-Jung WANG
  • Patent number: 10290730
    Abstract: A semiconductor power device includes an engineered aluminum-nitride substrate structure, and method of fabricating the same are described. The engineered substrate structure is effectively integrated with a transition layer of AlN/AlGaN disposed thereon, a buffer layer disposed on the transition layer having a C—(Al)GaN/u-GaN multiple stacking layered structure, a channel layer, a barrier layer, and an optional SiNx interlayer together, to form a GaN-based semiconductor power device. The GaN buffer layer is capable of achieving sufficient thickness for higher performance. The engineered substrate structure has a core region made of an aluminum nitride (AlN) substrate, a single crystal silicon layer as top material layer thereof, and bonded together with an encapsulated multi-layered structure containing adhesive layers, thin film layers and the AlN substrate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Epistar Corporation
    Inventors: Ya-Yu Yang, Yu-Jiun Shen, Chia-Cheng Liu
  • Publication number: 20190103482
    Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU