Patents by Inventor Chia-Cheng Liu

Chia-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293578
    Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 15, 2022
    Inventors: Wei-Cheng CHU, Ming-Fu JIANG, Chia-Cheng LIU, Chih-Yuan LEE
  • Patent number: 11380661
    Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 5, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Chih-Yuan Lee
  • Patent number: 11348831
    Abstract: A semiconductor assembly manufacturing method includes: providing a substrate including a first conductive circuit; disposing a first electronic component on a side of the substrate; forming a first plastic seal layer covering the substrate and the first electronic component; setting up a plurality of grooves in the first plastic seal layer, the groove exposes at least a portion of the first conductive circuit of the substrate; and filling a conductive material in each of the grooves by vacuum printing so as to form a second conductive circuit electrically connected to the first conductive circuit of the substrate, and a second electronic component pad position thereof in the first plastic seal layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 31, 2022
    Assignee: UNIVERSAL GLOBAL TECHNOLOGY (SHANGHAI) CO., LTD
    Inventors: Chia-Cheng Liu, Xiao-Lei Zhou
  • Publication number: 20210359123
    Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU
  • Patent number: 11145621
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Chia-Cheng Liu, Chien-Feng Chan
  • Publication number: 20210298181
    Abstract: An electronic device includes a flexible circuit structure. The flexible circuit structure includes a flexible substrate and an insulator. The flexible substrate has a surface on which a plurality of pads are disposed. The insulator is disposed on the flexible substrate and is disposed between two adjacent pads of the plurality of pads.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 23, 2021
    Inventors: Wei-Cheng CHU, Chia-Cheng LIU, Ming-Fu JIANG
  • Patent number: 11094814
    Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 17, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Ya-Yu Yang, Shang-Ju Tu, Tsung-Cheng Chang, Chia-Cheng Liu
  • Patent number: 11049961
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 29, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shang-Ju Tu, Chia-Cheng Liu, Tsung-Cheng Chang, Ya-Yu Yang, Yu-Jiun Shen, Jen-Inn Chyi
  • Publication number: 20210088060
    Abstract: An assembled-type fastener unit includes a base, a handling member movably fitted in the base, and a locking device movably received in the handling member. The handling member can be operated for the locking device to extend out of the base to form a locked state or for the locking device to retract into the base to form an unlocked state. To use the fastener unit, the base is firstly connected to an object. Then, the handling member is operated for the locking device to extend out of the base and lock to a target object to form the locked state; or the handling member can be operated for the locking device to retract into the base to separate from a target object and form the unlocked state. Thus, at least two objects can be repeatedly and quickly connected to or disconnected from one another using the fastener unit.
    Type: Application
    Filed: August 19, 2020
    Publication date: March 25, 2021
    Inventors: TING-JUI WANG, CHIA-CHENG LIU
  • Publication number: 20210005512
    Abstract: A semiconductor assembly manufacturing method includes: providing a substrate including a first conductive circuit; disposing a first electronic component on a side of the substrate; forming a first plastic seal layer covering the substrate and the first electronic component; setting up a plurality of grooves in the first plastic seal layer, the groove exposes at least a portion of the first conductive circuit of the substrate; and filling a conductive material in each of the grooves by vacuum printing so as to form a second conductive circuit electrically connected to the first conductive circuit of the substrate, and a second electronic component pad position thereof in the first plastic seal layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 7, 2021
    Inventors: CHIA-CHENG LIU, XIAO-LEI ZHOU
  • Patent number: 10825787
    Abstract: A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 ?m and less than or equal to 14 ?m. In addition, the disclosure further provides an electronic device including the first electronic element.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 3, 2020
    Assignee: Innolux Corporation
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Tong-Jung Wang
  • Patent number: 10820425
    Abstract: A display device is provided. The display device includes a display panel, a flexible circuit board, an integrated circuit, and a conductive layer. The flexible circuit board is electrically connected with the display panel and includes a plurality of conductive wires. The integrated circuit is disposed on the flexible circuit board and has a plurality of bumps. The conductive layer is disposed between the integrated circuit and the flexible circuit board and covers a periphery of the integrated circuit. In addition, the conductive layer includes an adhesive and a plurality of conductive particles distributed in the adhesive. Moreover, the bumps are electrically connected with the conductive wires through the conductive particles.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 27, 2020
    Assignee: Innolux Corporation
    Inventors: Wei-Cheng Chu, Chia-Cheng Liu, Chih-Yuan Lee, Chin-Lung Ting, Tong-Jung Wang
  • Publication number: 20200312828
    Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Inventors: Wei-Cheng CHU, Ming-Fu JIANG, Chia-Cheng LIU, Chih-Yuan LEE
  • Patent number: 10734509
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Epistar Corporation
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Patent number: 10720415
    Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 21, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Chih-Yuan Lee
  • Patent number: 10651003
    Abstract: An ion implanting method includes providing a gas having a bonding energy ranged from about 220 kJ/mol to about 450 kJ/mol; ionizing the gas to form a plurality of types of ions; and directing at least one of the types of the ions to implant a substance. The gas includes at least one of N2H4, CH3N2H3, C6H5N2H3, CFCl3 and C(CH3)3F.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Ying Tsai, Ming-Hui Li, Chia-Cheng Liu
  • Publication number: 20200006543
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Shang-Ju TU, Chia-Cheng LIU, Tsung-Cheng CHANG, Ya-Yu YANG, Yu-Jiun SHEN, Jen-Inn CHYI
  • Publication number: 20190378817
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Chia-Cheng LIU, Chien-Feng CHAN
  • Publication number: 20190341479
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: SHANG JU TU, YA YU YANG, CHIA CHENG LIU, TSUNG CHENG CHANG
  • Publication number: 20190306990
    Abstract: A display device is provided. The display device includes a display panel, a flexible circuit board, an integrated circuit, and a conductive layer. The flexible circuit board is electrically connected with the display panel and includes a plurality of conductive wires. The integrated circuit is disposed on the flexible circuit board and has a plurality of bumps. The conductive layer is disposed between the integrated circuit and the flexible circuit board and covers a periphery of the integrated circuit. In addition, the conductive layer includes an adhesive and a plurality of conductive particles distributed in the adhesive. Moreover, the bumps are electrically connected with the conductive wires through the conductive particles.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: Innolux Corporation
    Inventors: Wei-Cheng Chu, Chia-Cheng Liu, Chih-Yuan Lee, Chin-Lung Ting, Tong-Jung Wang