Patents by Inventor Chia-Cheng Wu

Chia-Cheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230033343
    Abstract: An electronic device including a substrate, a signal line, and a spacer is provided. The signal line is disposed on the substrate and includes at least one curve segment. The spacer is disposed on the substrate and is disposed corresponding to the at least one curve segment.
    Type: Application
    Filed: June 7, 2022
    Publication date: February 2, 2023
    Applicant: Innolux Corporation
    Inventors: You-Cheng Lu, Yung-Hsun Wu, Chia-Hao Tsai, Yi-Shiuan Cherng
  • Patent number: 11567290
    Abstract: An optical member driving mechanism for driving an optical member having an optical axis is provided, including a fixed portion, a movable portion, a first elastic member, and a driving assembly. The movable portion is configured to hold the optical member, and is movably connected the fixed portion via the first elastic member. The driving assembly drives the movable portion to move along the optical axis within a range of motion. The range of motion includes a first limit moving range and a second limit moving range. The first limit moving range is the maximum distance that the movable portion can move toward the light-entering side, and the second limit moving range is the maximum distance that the movable portion can move toward the light-emitting side. When the movable portion is in a predetermined position, the first limit moving range is greater than the second limit moving range.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 31, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Shang-Yu Hsu, Yu-Cheng Lin, Yung-Ping Yang, Wen-Yen Huang, Tsung-Han Wu, Yi-Chun Cheng, Chen-Chi Kuo, Chia-Hsiu Liu, Ichitai Moto, Sin-Jhong Song
  • Patent number: 11563120
    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
  • Patent number: 11561649
    Abstract: An operation judgment method for an interactive touch system, which is applied by a first electronic device in cooperation with a second electronic device. The first electronic device receives a projected image from the second electronic device. The projected image is displayed on a display surface of the first electronic device. The operation judgment method includes steps S1 to S3. Step S1 generates a plurality of touch feature information corresponding to a plurality of touchpoints according to a touch action. Each touch feature information includes a plurality of eigenvalues, and the touch feature information is stored in a touch register module, wherein the first touch feature information of each touch action is the initial touchpoint. Step S2 sequentially analyzes the touch feature information to generate a first command or a second command. Step performs a corresponding operation according to the first command or the second command.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: January 24, 2023
    Assignee: AVER INFORMATION INC.
    Inventors: Chao-Hung Chang, Chia-Feng Wu, Yun-Long Sie, Cheng-Cheng Yu
  • Publication number: 20230010065
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui
  • Publication number: 20220415275
    Abstract: The disclosure provides a display device and another display device. The display device includes a display panel. The display panel has a functional display area. The functional display area includes a pixel. The pixel includes a white pixel and multiple display pixels. The display pixels surround at least a part of the white pixel, and the white pixel includes a pixel electrode. The another display device includes another display panel. The another display panel has a functional display area, and the functional display area includes a pixel and a signal line. The pixel includes a white pixel and multiple display pixels. The signal line includes a branch, and the branch is electrically connected to one of the display pixels. The display device and the another display device of the disclosure is capable of reducing the problem of diffraction or having a better optical sensing effect.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 29, 2022
    Applicant: Innolux Corporation
    Inventors: Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yu-Shih Tsou, You-Cheng Lu, Yung-Hsun Wu
  • Publication number: 20220413763
    Abstract: A mapping information management method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command instructing storing of first data from a host system; storing the first data to a rewritable non-volatile memory module according to the write command; updating mapping information corresponding to the storing of the first data; storing the mapping information to the rewritable non-volatile memory module; generating assistant information according to first part information of the mapping information, where the assistant information is not stored into the rewritable non-volatile memory module; and transmitting second part information of the mapping information and the assistant information to the host system to provide information related to the storing of the first data.
    Type: Application
    Filed: July 19, 2021
    Publication date: December 29, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hung Chien, Yi-Cheng Wu, Chia-Hsiang Cheng
  • Publication number: 20220406652
    Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yu YANG, Po-Wei LIU, Yun-Chi WU, Yu-Wen TSENG, Chia-Ta HSIEH, Ping-Cheng LI, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20220406592
    Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: December 22, 2022
    Inventors: Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11526081
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Patent number: 11523333
    Abstract: The present invention discloses a method for pairing and interconnecting electronic devices, which cooperates with at least two electronic devices that are grouped as a transmitting end and a receiving end respectively, and the transmitting end operates in a first mode. The method for pairing and interconnecting electronic devices comprises at least Step 1 to Step 4. Step 1 refers to searching any available transmitting end in a wireless manner by the receiving end, and displaying a connection name of the transmitting end on the receiving end. Step 2 refers to prompting a dynamic operating instruction by the receiving end. Step 3 refers to executing operation by the transmitting end based on the dynamic operating instruction and thereby issuing an action instruction. Step 4 refers to receiving the action instruction by the receiving end, and establishing a connection with the transmitting end which issues the action instruction.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 6, 2022
    Assignee: AVER INFORMATION INC.
    Inventors: Chao-Hung Chang, Chia-Feng Wu, Jhan-Jhang Liao, Lien-Kai Chou, Cheng-Cheng Yu, Cheng-Mou Tsai, Li-Hsueh Yang
  • Publication number: 20220384247
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure which has a first corner. The semiconductor device also includes a first well region with a first conductive type. The semiconductor device includes further includes a gate structure over the first well region and covers a portion of the first corner of the first isolation structure. In addition, the semiconductor device includes a first doped region and a second doped region disposed on two opposites of the gate structure. Each of the first doped region and the second doped region has the first conductive type. The semiconductor device also includes a first counter-doped region in the first well region with a second conductive type different from the first conductive type. The first counter-doped region covers the first corner of the first isolation structure.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: CHIA-CHEN CHANG, YUAN-CHENG YANG, YUN-CHI WU
  • Publication number: 20220382069
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Hsin-Yu CHEN, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
  • Publication number: 20220373815
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen-Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20220367632
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220356571
    Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Peng-Cheng HONG, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Patent number: 11495687
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Publication number: 20220350211
    Abstract: A display device having a first region, a second region, and a third region set between the first region and the second region is provided. The display device includes a first sub-pixel, a second sub-pixel, and a first signal line. The first sub-pixel is arranged in the first region. The second sub-pixel is arranged in the second region, the area of the first sub-pixel is larger than the area of the second sub-pixel. The first signal line is arranged in the first region and the third region, and is electrically connected to the first sub-pixel and the second sub-pixel. At least a part of the first signal line extends in the first direction in the first region. At least another part of the first signal line extends in the second direction in the third region. The first direction is different from the second direction.
    Type: Application
    Filed: April 1, 2022
    Publication date: November 3, 2022
    Applicant: Innolux Corporation
    Inventors: You-Cheng Lu, Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yung-Hsun Wu
  • Publication number: 20220352223
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Publication number: 20220344504
    Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
    Type: Application
    Filed: November 10, 2021
    Publication date: October 27, 2022
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN