Abstract: A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Abstract: Power flow models of Interline Power Flow Controllers (IPFC) for large-scale power systems are studied, in details. Mathematical models of the IPFC, using the d-q axis decompositions of control parameters are derived. In this framework, for each IPFC, only two control parameters are added to the unknown vector in the iteration formula and the quadratic convergence characteristic is preserved. Simulations results from several practical large-scale power systems embedded with multiple Convertible Static Compensators (CSCs) demonstrate the effectiveness of the proposed models. Comparisons with existing models are made to elucidate the performance of the convergence.

Abstract: A new method of searching paths that are suffering ESD is proposed in this invention, improving the design flow of a VLSI circuit and reducing the cost of designing the ESD circuits in a whole chip, comprising three parts, the circuit flattening, the closure algorithm, and the supernode algorithm. The objective is to find the paths satisfying the following two constraints: (1) only one edge connected to the gate pin and the source (or drain) pin is allowed; (2) only the head-node and the tail-node in a path could be the pin of top-level circuit. Two algorithms in this invention are the closure algorithm that uses the closure property in the ?1/0/1 matrix multiplication so that the connective property of nodes can be observed after several matrix self-multiplication, and the supernode algorithm.

Abstract: A new method for MIMO RLCG interconnects model order reduction technique using the global Arnoldi algorithm is proposed that is an extension of the standard Arnoldi algorithm for MIMO systems. Under this framework, the input matrix serves as a stacked vector form and the global Arnoldi algorithm will be the standard Arnoldi algorithm applied to a new matrix pair. This new matrix Krylov subspace from the Frobenius orthonormalization process is the union of system moments. By employing the congruence transformation with this matrix Krylov subspace, the one-sided projection method can be used to construct a reduced-order system. Connections of the reduced system and the original RLCG interconnect circuits are developed. The transfer matrix residual error of reduced system is derived analytically. This error information will be a guideline for the order selection scheme. Experimental results demonstrate the feasibility and the effectiveness of the proposed method.

Abstract: A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

Abstract: Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

Abstract: A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, the inserted buffers location information, the wire electrical parameters and a buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, the clock delay and the clock skew can be obtained. Finally, using the method, a modified clock tree netlist satisfying the timing specifications can be constructed.

Abstract: A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method includes embedding a developed tool into an existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics quickly judge if the problem has corresponding feasible solutions and searching the optimal solution. Modified data from the given scan chain declaration data and the scan pattern data, which satisfy the constraints, can be obtained.

Abstract: A method for calculating power flow solution of a power transmission network with unified power flow controllers is adapted to calculate the power flow on a large-scale power transmission network. The unified power flow controller has a series transformer, a series converter, a direct current coupling capacitor, a shunt converter, and a series transformer. The shunt transformer is connected electrically to a sending-end bus. The series transformer is connected electrically to the sending-end bus and a receiving-end bus. The unified power flow controller is represented by equivalent active and reactive loads on the sending-end and receiving-end buses of the power transmission network.

Abstract: An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm.

Abstract: Power flow models of Interline Power Flow Controllers (IPFC) for large-scale power systems are studied, in details. Mathematical models of the IPFC, using the d-q axis decompositions of control parameters are derived. In this framework, for each IPFC, only two control parameters are added to the unknown vector in the iteration formula and the quadratic convergence characteristic is preserved. Simulations results from several practical large-scale power systems embedded with multiple Convertible Static Compensators (CSCs) demonstrate the effectiveness of the proposed models. Comparisons with existing models are made to elucidate the performance of the convergence.

Abstract: Two-sided projection-based model reductions has become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered as a stopping criteria to terminate the non-symmetric Lanczos iteration process. Furthermore, it can be found that the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves at most rank-2 modification at the previous step of the non-symmetric algorithm. The information of stopping criteria will provide a guideline for the order selection scheme used in the Lanczos model-order reduction algorithm.

Abstract: The power flow model of the multiterminal voltage-source converter-based high voltage DC (M-VSC-HVDC) transmission system for large-scale power systems is studied. The mathematical model is derived using the d-q axis decomposition of HVDC's control parameter. The developed model can be applied to all existing shunt voltage-source converter (VSC) based controllers, including Static Synchronous Compensator (STATCOM), point-to-point HVDC system, back-to-back HVDC system and multiterminal HVDC system. A unified procedure is developed for incorporating the proposed model into the conventional Newton-Raphson power flow solver. The IEEE 300-bus test system embedded with multiple HVDC transmission systems under different configurations are investigated. Simulation results reveal that the proposed model is effective and accuracy in meeting various control objectives.

Abstract: A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects models high-speed VLSI interconnects as lumped RLG coupled frees. An inductive crosstalk noise waveform can be accurately estimated in an efficient manner using a linear time moment computation technique in conjunction with a projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived taking into consideration of both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for use in crosstalk estimations.

Abstract: A method for calculating power flow solution of a power transmission network with unified power flow controllers is adapted to calculate the power flow on a large-scale power transmission network. The unified power flow controller has a series transformer, a series converter, a direct current coupling capacitor, a shunt converter, and a series transformer. The shunt transformer is connected electrically to a sending-end bus. The series transformer is connected electrically to the sending-end bus and a receiving-end bus. The unified power flow controller is represented by equivalent active and reactive loads on the sending-end and receiving-end buses of the power transmission network.

Abstract: The work proposes a model reduction method, the rational Arnoldi method with adaptive orders (RAMAO), to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Abstract: A method for efficiently estimating crosstalk noise of nanometer VLSI interconnects is provided. In the invention, nanometer VLSI interconnects are modeled as nonuniform distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

Abstract: The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This paper extends this technique for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposal method.

Abstract: A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.