Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

Abstract: Given the current operating condition at each bus from real-time database, from the short-term load forecast, or from near-term generation dispatch, we present a method for real-time contingency prediction and selection in current energy management systems. This method can be applied to contingency prediction and selection for the near-term power system in terms of load margins to collapse and of the bus voltage magnitudes. The propose algorithm uses only two tangent vectors of power flow solutions and curve fitting based techniques to perform look-ahead load margin and voltage magnitude simultaneously. Therefore, it can overcome the traditional snap-shot contingency analysis methods. Simulations are performed on IEEE 57 and 118-bus test systems to demonstrate the feasibility of this method.

Abstract: A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results have demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

Abstract: A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, inserted buffers locations information, wires electrical parameters and buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, clock delay and clock skew can be obtained. Finally using the proposed method, a modified clock tree netlist which satisfying the timing specifications can be constructed.

Abstract: A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

Abstract: A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects is provided. In the invention, high-speed VLSI interconnects are modeled as lumped RLC coupled trees. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

Abstract: A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Abstract: A method for reordering a scan chain so that the given constraints are met and the peak power dissipation is minimized and disclosed. The constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The developed tool can be embedded into the existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics are quickly judging if the problem has corresponding feasible solutions and searching the optimal solution. Given the scan chain declaration data and the scan pattern data, the modified ones, which satisfy the constraints, can be obtained.

Abstract: A method and apparatus for model-order reduction and sensitivity analysis of VLSI interconnect circuits, is disclosed. It has been known that reduced-order models can be yielded using the congruence transformation, which contains information of circuit moments of both circuit network and its corresponding adjoint network. By exploring symmetric properties of the modified nodal analysis (MNA) formulation, the method needs only half of the system moment information compared with the previous ones. Passivity of the reduced-order model is still preserved. The relationship between the adjoint network and the sensitivity analysis will also be disclosed.