Abstract: A cutting and attaching system for a screen protector having a high hardness is provided, and includes a cutting apparatus, a universal sheet having a hardness of at least 5H, and a film applicator. The cutting apparatus can perform a cutting process to the universal sheet through a cutter thereof according to the film applicator and a mobile apparatus, thereby forming a screen protector that is suitable to be applied to the film applicator and the mobile apparatus.

Abstract: An integrated substation is provided. The integrated substation includes a cabinet and at least one airflow driver. The cabinet has a high pressure room, a low pressure room, and an exchange room located between the high pressure room and the low pressure room. The exchange room and the high pressure room are separated from each other by a first inner wall, and the exchange room and the low pressure room are separated from each other by a second inner wall.

Abstract: Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a metal-all-around contact structure coupled with an S/D region are described herein. In one example, an IC structure may include a region of a doped semiconductor material. An IC structure may include a stack of nanoribbons of a semiconductor material including first portions and second portions on either side of the region, wherein the first portions are in contact with a first side of the region and the second portions are in contact with a second side of the region. An IC structure may include a conductive material over portions of the region between the first side and the second side in a same layer as at least one of the nanoribbons of the stack.

Abstract: An IC device may have active regions and one or more isolation regions. The IC device includes gates that are in parallel. One or more semiconductor structures (e.g., fins, nanoribbons, etc.) may extend across each gate in the IC device. Some of the gates are in the active regions. The other gates are in the isolation region. A gate in an active region may be between semiconductor regions, which may function as the source region and drain region of a transistor. A gate in an isolation region may be between insulator regions. The insulator regions may be formed from the backside of the IC device. For instance, semiconductor regions may be formed in both the active regions and the isolation regions. The semiconductor regions in the regions designated to be isolation regions may be removed from the backside and filled with one or more electrical insulators.

Abstract: An IC device may have activation regions and an isolation region between the active regions. An active region may include one or more transistors. The IC device includes gates that are in parallel. Some of the gates are in the active regions. The other gates are in the isolation region. A source or drain region may be formed between a gate in the isolation region and a gate in a transistor in the first direction. The IC device may include one or more semiconductor structures that extend across a gate in a transistor, and the semiconductor structures may constitute a channel region of the transistor. The IC device may also include one or more semiconductor structures that extend across an individual gate in the isolation region. An insulative structure may be formed between two gates in the isolation region. The insulative structure may be over the source or drain region.

Abstract: An IC device may include a support structure and a transistor built based on the support structure. The transistor may include an electrical contact over a semiconductor region in the transistor. The electrical contact may be a single structure formed by filling a single opening region with a conductive material. In an example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a deep via. The deep via may extend through the support structure and contact a backside metal layer for delivering power or signal to the semiconductor region. In another example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a semiconductor region in another transistor. A dielectric structure may be between the two semiconductor regions.

Abstract: Fabrication methods for integrated circuit (IC) structures and devices including asymmetric source and drain regions are described herein. In one example, an integrated circuit structure includes a transistor including a first region and a second region, where one of the first region and the second region is a source region of the transistor, and another of the first region and the second region is a drain region of the transistor, and where the first and second regions have different widths. In one example, the first region has a first width and the second region has a second width that is smaller than the first width.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a conductive via with front-side and back-side connections with an S/D region are described herein. In one example, an IC structure includes a conductive via extending between a first layer and a second layer and an S/D region of a transistor between the first layer and the second layer, where the S/D region includes a first semiconductor material and a second semiconductor material. In one such example, the second semiconductor material may be epitaxially grown on the first semiconductor material of the S/D region from a back side of the IC structure. Conductive elements in layers over and under the conductive via may couple the conductive via with the S/D region from both the front-side and back-side S/D contact structures.

Abstract: Fabrication methods for integrated circuit (IC) structures and devices with different nanoribbon thicknesses are disclosed. In one example, an IC structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.

Abstract: A transformer monitoring management system includes multiple smart regulating transformers and a backend management system, and is applicable to a smart gird that includes a transmission and distribution network and a communication infrastructure. Each smart regulating transformer includes a transformer body coupled to the transmission and distribution network, a voltage regulator, and a monitoring terminal. A detecting module is disposed on the transformer body to obtain operation status data that includes a voltage and a current of a low-voltage side. The voltage regulator is coupled to the transformer body, so that the voltage of the low-voltage side is compensated to be within a rated voltage range. The monitoring terminal is coupled to the detecting module for collecting the operation status data and generating an abnormal status message, and transmits the operation status data or the abnormal status message to the backend management system through the communication infrastructure.

Abstract: A segmentation model training method is disclosed. The segmentation model includes the following operations: inputting several first sample groups of a large sample set to a data augmentation model to generate several augmentation sample groups; generating several mix sample groups based on several second sample groups of a small sample set; inputting several mix sample groups to the data augmentation model to generate several augmentation mix sample groups; and training a segmentation model according to several augmentation sample groups and several augmentation mix sample groups, including: performing pre-training to the segmentation model according to several augmentation sample groups; and performing fine-tuning training to the segmentation model corresponding to several augmentation mix sample groups.

Abstract: The present disclosure relates to a power grid system and method of managing the same. According to the present invention, a power grid system is provided. The power grid system is adapted to supply electric power to at least one load unit, and the power grid system comprises a bus, a switching module, and an energy storage system coupled to the bus. The at least one load unit is coupled to the bus. The switching module comprises a switching device. The switching device is connected between the bus and a main grid. The energy storage system is configured to operate in a current source mode and a voltage source mode, and it is configured to receive a tripped signal from the switching module. The energy storage system is configured to switch to the voltage source mode when the energy storage system receives the tripped signal.

Abstract: A self-diagnosing system including a communication diagnosing model, a device communication-status identification model, a communication-line identification model, and a graphic updating model is disclosed. The communication diagnosing model determines whether device data of each peripheral device is received. The device communication-status identification model identifies the communication-line of the peripheral device to be normal when the device data is received and determines whether a connection status of the peripheral device is a first category or a second category based on a target data. The communication-line identification model identifies the peripheral device to be offline when the device data is not received and inspects the communication-line of the peripheral device to determine whether the connection status of the peripheral device is the second category or a third category.

Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure.

Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: The disclosed system may include an antenna feed that has various electronic components. The system may also include a lens that has one or more layers, and an antenna embedded on at least a portion of the layers of the lens. The antenna may be electrically connected to at least one of the electronic components of the antenna feed. Various other apparatuses, wearable electronic devices, and methods of manufacturing are also disclosed.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.