Patents by Inventor Chia-Ching Lin

Chia-Ching Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376155
    Abstract: Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
    Type: Application
    Filed: August 26, 2020
    Publication date: December 2, 2021
    Inventors: Che-Lun Chang, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20210376094
    Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.
    Type: Application
    Filed: March 12, 2021
    Publication date: December 2, 2021
    Inventors: Yen-Po Lin, Wei-Yang Lee, Yuan-Ching Peng, Chia-Pin Lin, Jiun-Ming Kuo
  • Patent number: 11189654
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20210358811
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20210353703
    Abstract: A composition of plant ingredients, a herbal composition for inhibiting coronavirus and cytokine storm, and a preparation method of the herbal composition are introduced. The composition of plant ingredients has Heartleaf Houttuynia, Indigowoad Root, Fineleaf Nepeta, Saposhnikovia Root, Mulberry Leaf, Scutellaria Root, Mongolian Snakegourd Fruit, Magnolia Bark, Peppermint Herb and Baked Liquorice Root. The herbal composition has 1 to 20 parts by weight of Heartleaf Houttuynia, Indigowoad Root, Fineleaf Nepeta, Saposhnikovia Root, Mulberry Leaf, Scutellaria Root, Mongolian Snakegourd Fruit, Magnolia Bark, Peppermint Herb and Baked Liquorice Root.
    Type: Application
    Filed: December 21, 2020
    Publication date: November 18, 2021
    Inventors: YI-CHANG SU, WEN-HUI CHIOU, YAO-HAUR KUO, KENG-CHANG TSAI, CHIA-CHING LIAO, WEN-CHI WEI, CHUN-TANG CHIOU, KUO-MING YEH, YI-CHIA HUANG, CHIEN-JUNG LIN, JUI-SHAN LIN
  • Patent number: 11172080
    Abstract: A peripheral includes a body, an image processing device and a processor. The body includes a sub-housing and a second button. The sub-housing includes a control component. The control component includes a first button disposed on an upper surface of the sub-housing. The second button and the first button are disposed on different adjacent surfaces. The image processing device is disposed above or in the body. The image processing device is disposed above the body. The processor controls a first signal generated by the first button to be the same as a first signal generated by the second button. The sub-housing is disposed on an upper lateral side of the body.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 9, 2021
    Assignee: AVISION INC.
    Inventors: Shao-Lan Sheng, Chia-Ching Lin, Xiang Chi Lee
  • Publication number: 20210343856
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Application
    Filed: June 1, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20210343578
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.
    Type: Application
    Filed: January 15, 2021
    Publication date: November 4, 2021
    Inventors: Che-Lun Chang, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20210309469
    Abstract: An image forming device includes a case whereon a medium gateway opening is formed, and a tray assembly. The tray assembly includes a tray, a cover and a resilient component. The tray drives the cover to pivot relative to the case in a first pivoting direction from a second folding position to a second using position to reveal the medium gateway opening when the tray pivots relative to the case in the first pivoting direction from a first folding position to a first using position. When the tray pivots relative to the case in a second pivoting direction opposite to the first pivoting direction from the first using position to the first folding position, the cover is driven by the resilient component to pivot relative to the case in the second pivoting direction from the second using position to the second folding position to conceal the medium gateway opening.
    Type: Application
    Filed: March 9, 2021
    Publication date: October 7, 2021
    Inventor: Chia-Ching Lin
  • Publication number: 20210305398
    Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Nazila Haratipour, Tanay Gosavi, I-Cheng Tung, Seung Hoon Sung, Ian Young, Jack Kavalieros, Uygar Avci, Ashish Verma Penumatcha
  • Publication number: 20210272848
    Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 2, 2021
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20210273103
    Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.
    Type: Application
    Filed: July 31, 2020
    Publication date: September 2, 2021
    Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20210263460
    Abstract: An image forming device includes a casing and a medium detecting mechanism. A medium entrance is formed on the casing. The medium detecting mechanism includes a detector, a first pivoting component, a second pivoting component and a resilient component. When at least one medium enters into the medium entrance and abuts against the first pivoting component, the at least one medium drives the first pivoting component to pivot in a first pivoting direction, so that the second pivoting component is driven by the resilient component to pivot in the first pivoting direction to actuate the detector for generating a signal. When the second pivoting component is stopped from pivoting in the first pivoting direction, deformation of the resilient component allows the first pivoting component to be driven by the at least one medium to pivot relative to the second pivoting component in the first pivoting direction continuously.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 26, 2021
    Inventor: Chia-Ching Lin
  • Patent number: 11069609
    Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Jasmeet S. Chawla, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol
  • Patent number: 11063131
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Patent number: 11015825
    Abstract: An intelligent air-drying system and method are provided. The intelligent air-drying system includes an air-drying device and an application program. The air-drying device includes a device body, a sensing unit, a heater, and a processing unit. The device body has a water-absorbing material for absorbing moisture in the air. The sensing unit is disposed on the device body to detect the humidity of the environment where the air-drying device is located. The heater is disposed on the device body to heat the water-absorbing material. The processing unit is coupled to the sensing unit and the heater, and the processing unit executes the application program. The startup timing of the heater is dynamically predicted based on the daily humidity change measured by the sensing unit, and the heater is started before the water-absorbing material reaches saturation to ensure the water-absorbing and dehumidifying capabilities of the water-absorbing material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: May 25, 2021
    Assignee: FORTUNE ELECTRIC CO., LTD.
    Inventors: Chia-Ching Lin, Ching-Min Chen
  • Patent number: 10998495
    Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10957844
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Sasikanth Manipatruni, Robert L. Bristol, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20210018197
    Abstract: An intelligent air-drying system and method are provided. The intelligent air-drying system includes an air-drying device and an application program. The air-drying device includes a device body, a sensing unit, a heater, and a processing unit. The device body has a water-absorbing material for absorbing moisture in the air. The sensing unit is disposed on the device body to detect the humidity of the environment where the air-drying device is located. The heater is disposed on the device body to heat the water-absorbing material. The processing unit is coupled to the sensing unit and the heater, and the processing unit executes the application program. The startup timing of the heater is dynamically predicted based on the daily humidity change measured by the sensing unit, and the heater is started before the water-absorbing material reaches saturation to ensure the water-absorbing and dehumidifying capabilities of the water-absorbing material.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Inventors: CHIA-CHING LIN, CHING-MIN CHEN