Abstract: The disclosed system may include a support structure, a lens mounted to the support structure, where the lens includes at least one conductive layer that includes conductive material, and an antenna disposed on the support structure within a specified maximum distance from the lens. Various characteristics of the lens or the antenna may be modified to reduce coupling between the antenna and the layer of conductive material in the lens. Various other wearable devices, apparatuses, and methods of manufacturing are also disclosed.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

Abstract: A high-entropy transition metal layered oxide is an O3 type high-entropy transition metal layered oxide which is represented by the following formula (1): Na[NiaFebMncM1dM2e]O2??(1). In the formula (1), M1 and M2 are selected from a group consisting of V, Cr, Co, Cu, Zn, and Ti, a+b+c+d+e=1, 0.05?a?0.35, 0.05?b?0.35, 0.05?c?0.35, 0.05?d?0.35, and 0.05?e?0.35.

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

Abstract: A measuring equipment, applied to carry a workpiece to be measured, includes a main base and a positioning device. The main base includes a measuring center axis. The positioning device includes at least two positioning elements. Each of the at least two positioning elements is disposed movably on the main base, and each of the at least two positioning elements is moved with respect to the measuring center axis. An identical distance is there from each of the at least two positioning elements to the measuring center axis. Each of the at least two positioning elements is used for the workpiece to contact and to be positioned to the measuring center axis.

Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.

Abstract: Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.

Abstract: In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.