Patents by Inventor Chia Chiu
Chia Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11799189Abstract: In one example, an electronic device may include a housing having an opening and an antenna assembly disposed in the housing. The antenna assembly may include an antenna mounted to the housing, an antenna module disposed corresponding to the opening, and a cable to connect the antenna to the antenna module via routing the cable through the opening.Type: GrantFiled: July 19, 2018Date of Patent: October 24, 2023Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yu Chen So, Ju-Hung Chen, Lien-Chia Chiu, Hao Ming Chen
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Publication number: 20230335449Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: June 17, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
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Patent number: 11764475Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.Type: GrantFiled: August 24, 2021Date of Patent: September 19, 2023Assignee: MEDIATEK INC.Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin
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Patent number: 11732511Abstract: An information handling system locks to a display stand and/or an external object with a locking mount coupled to the display stand having a Kensington lock and a padlock. The locking mount has a lock switch with an unlocked position to accept and release the information handling system securing members and a lock position that engages the securing members with a lock plate to prevent removal of the information handling system. In the unlocked position, the Kensington lock and padlock loop are unavailable for securing the information handling system. In the locked position, the Kensington lock slot is unblocked to accept a securing cable and the padlock loop will extend from a retract position to accept a padlock. When a cable fits in the slot and/or a padlock fits in the padlock loop, the lock switch is engaged in the locked position to prevent removal of the information handling system securing members.Type: GrantFiled: April 22, 2022Date of Patent: August 22, 2023Assignee: Dell Products L.P.Inventors: Kok Lian Lim, Cheng-Chia Chiu, Chao-Long Chou, Kerk Inn Pin Augustine
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Patent number: 11721602Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.Type: GrantFiled: May 6, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
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Publication number: 20230246664Abstract: The present invention discloses an expansion structure for an electronic card for installing the electronic card. The expansion structure includes a carrier board, a limiting member and a fixing element. The carrier board carries the electronic card. The limiting member includes a sidewall and a blocking piece extended from the sidewall, the sidewall is formed on one side of the carrier board, and the sidewall, the blocking piece and the carrier board jointly define a sliding channel for accommodating the electronic card. The fixing element fixes the electronic card at the carrier board. Thus, a small-size electronic card can be installed on an installation interface of a large-size electronic card by the expansion structure, achieving the effect of sharing the same installation interface.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: KUANG-YEH CHANG, YI-CHIA CHIU
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Publication number: 20230236222Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.Type: ApplicationFiled: March 30, 2023Publication date: July 27, 2023Applicant: MEDIATEK INC.Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Sheng-Wei Lei, Chang-Lin Wei, Che-Hsien Huang, Shih-Chia Chiu, Yi-Chieh Lin, Wun-Jian Lin
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Patent number: 11682816Abstract: A filter circuit includes an input node, an output node, a first filtering element and a second filtering element. The first filtering element has a first terminal coupled to the input node and a second terminal, and is configured to provide a first signal conducting path toward the second terminal for conducting a first signal received at the input node to the second terminal. The second filtering element has a first terminal coupled to the input node and a second terminal, and is configured to provide a second signal conducting path toward the output node for conducting a second signal received at the input node to the output node. The second terminal of the first filtering element and the second terminal of the second filtering element are open-circuit terminals.Type: GrantFiled: July 27, 2020Date of Patent: June 20, 2023Assignee: MEDIATEK INC.Inventors: Yi-Chieh Lin, Shih-Chia Chiu
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Publication number: 20230187377Abstract: A semiconductor package includes a base film, a semiconductor die on the base film, metal studs on the semiconductor die, shielding pillars on the base film and around the semiconductor die, a first molding compound encapsulating the semiconductor die, the metal studs, and the shielding pillars, a first re-distribution structure on the first molding compound, a second molding compound on the first re-distribution structure, through-mold-vias in the second molding compound, and a second re-distribution structure on the second molding compound and electrically connected to the through-mold-vias. The second re-distribution structure comprises an antenna.Type: ApplicationFiled: November 16, 2022Publication date: June 15, 2023Applicant: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chih-Ming Hung, Shih-Chia Chiu
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Publication number: 20230154863Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
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Publication number: 20230055278Abstract: An example computing device includes a power switch, a power management device to control a power state change of the computing device based on a command from a power control device, and a controller. The controller is to, in response to receiving a power control request message from an external device, change the power control device from the power switch to the external device.Type: ApplicationFiled: March 9, 2020Publication date: February 23, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: Hou-Chu Su, Wei-Ming Tseng, Lien-Chia Chiu, Chien-Feng Chu
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Publication number: 20230054020Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.Type: ApplicationFiled: November 6, 2022Publication date: February 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
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Patent number: 11581268Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: GrantFiled: December 6, 2021Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
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Publication number: 20230014165Abstract: Example implementations relate to electrical traces on panels. In some examples, a display can include an on-cell touch (OCT) panel, a cover panel, and an electrical trace located on the cover panel, where the cover panel is a glass panel and the electrical trace is to transmit a signal from a component to a processor.Type: ApplicationFiled: December 13, 2019Publication date: January 19, 2023Inventors: Chung LIN CHEN, Hsiu-Pen LIN, Lien Chia CHIU, KUN CHENG TSAI
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Patent number: 11515229Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.Type: GrantFiled: March 31, 2020Date of Patent: November 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
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Patent number: 11501696Abstract: A pixel driving device includes a capacitance, a reset circuit, a compensation circuit, a driving transistor and a first transistor. Reset circuit and compensation circuit are coupled to a first end and a second end of capacitance. First transistor is coupled between second end of driving transistor and second end of capacitance. Reset circuit resets first end of capacitance at a power supply voltage and reset second end of capacitance at a reference voltage according to a first sweep signal respectively. Compensation circuit writes a data voltage into first end of capacitance via driving transistor and second end of capacitance is maintained at reference voltage according to a second sweep signal. First transistor generates a driving voltage difference between first end and second end of capacitance according to a control signal. Driving transistor outputs a current to a luminous element according to driving voltage difference.Type: GrantFiled: May 14, 2021Date of Patent: November 15, 2022Assignee: AU OPTRONICS CORPORATIONInventors: Chia-En Wu, Ming-Hsien Lee, Wei-Chia Chiu, Kuan-Yu Chen, Chia-Yen Lin
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Publication number: 20220359322Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
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Publication number: 20220302574Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: ApplicationFiled: April 4, 2022Publication date: September 22, 2022Applicant: MediaTek Inc.Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Patent number: 11322823Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: GrantFiled: September 3, 2018Date of Patent: May 3, 2022Assignee: MediaTek Inc.Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Publication number: 20220102859Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.Type: ApplicationFiled: August 24, 2021Publication date: March 31, 2022Applicant: MEDIATEK INC.Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin