Patents by Inventor Chia Chiu

Chia Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170820
    Abstract: A wireless communication circuit and an electronic device are provided. The wireless communication circuit used for an electronic device includes a wireless transceiver unit used to generate a transmitting signal, an impedance matching unit electronically coupled to the wireless transceiver unit, a coupling unit and a system grounding surface. The impedance matching unit includes at least one impedance, the impedance matching unit is used to convert the transmitting signal to a feeding signal according to the impedance value of at least one impedance. The coupling unit is electronically coupled to the impedance matching unit, to radiate the energy of the feeding signal. The system grounding surface is used to transmit a first electromagnetic wave signal via resonance on the plane of the system grounding surface after receiving the energy of the feeding signal.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 1, 2019
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Shih-Chia Chiu, Shih-Yuan Chen, Skye Hui-Hsin Wu, Chien-Hao Chiu, Wang-Ta Hsieh, Wei-Hsin Shih
  • Publication number: 20180261557
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 10068867
    Abstract: A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing pad over the connective layer. The forming the connective layer includes depositing a dielectric layer of a dielectric material over the die and patterning the dielectric layer. The patterning the dielectric layer includes forming a supporting pad area and forming a conductive channel area. A portion of the conductive channel area passes at least partially through the supporting pad area. At least one dielectric region interpose the portion of the conductive channel area and the supporting pad area. The forming the connective further includes filling the supporting pad area and the conductive channel area with a conductive material. The supporting pad area of the conductive material forms a supporting pad. The conductive channel area of the conductive material forms a conductive channel.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chia Chiu, Ming-Yen Chiu
  • Patent number: 9991586
    Abstract: A portable electronic device including a front cover, a back cover and a circuit board is provided. The circuit board is located between the front cover and the back cover. The back cover is combined with the front cover and includes a back section, a plurality of side sections and a separator, at least one of the side sections adjacent to the back cover includes a groove close to the back section and a slot far away from the back section, the slot is connected through to the groove, a first antenna unit and a second antenna unit are defined at the side section by the groove and the slot. The separator is located in the groove and the slot.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 5, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Chien-Ming Hsu, Wang-Ta Hsieh, Kuei-Shun Yeh, Shih-Chia Chiu, Chuan-Chien Huang
  • Patent number: 9972581
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 9941216
    Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Chien-Chia Chiu, Hsin-Chieh Huang, Tsung-Shu Lin, Pei-Ti Yu
  • Publication number: 20180068968
    Abstract: A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing pad over the connective layer. The forming the connective layer includes depositing a dielectric layer of a dielectric material over the die and patterning the dielectric layer. The patterning the dielectric layer includes forming a supporting pad area and forming a conductive channel area. A portion of the conductive channel area passes at least partially through the supporting pad area. At least one dielectric region interpose the portion of the conductive channel area and the supporting pad area. The forming the connective further includes filling the supporting pad area and the conductive channel area with a conductive material. The supporting pad area of the conductive material forms a supporting pad. The conductive channel area of the conductive material forms a conductive channel.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Chien-Chia Chiu, Ming-Yen CHIU
  • Patent number: 9836425
    Abstract: A computer apparatus, a datapath switching method and an associated method are provided. An operating system utilized by the computer apparatus is detected by an embedded controller, and datapaths for transmitting sensing signals to a platform controller hub are switched according to the operating system utilized by the computer apparatus by the embedded controller.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: December 5, 2017
    Assignee: Getac Technology Corporation
    Inventors: Yi-Chia Chiu, Chin-Jung Chang
  • Publication number: 20170345762
    Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.
    Type: Application
    Filed: September 29, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Chien-Chia Chiu, Hsin-Chieh Huang, Tsung-Shu Lin, Pei-Ti Yu
  • Patent number: 9818711
    Abstract: The semiconductor device includes a die that contains a substrate and a bond pad. A connective layer is disposed over the die. The connective layer includes a supporting pad and a conductive channel. A portion of the conductive channel passes at least partially through the supporting pad. At least one dielectric region is interposed between the supporting pad and the portion of the conductive channel.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chia Chiu, Ming-Yen Chiu
  • Patent number: 9748212
    Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Bor-Rung Su, Chang-Pin Huang, Chien-Chia Chiu, Hsien-Ming Tu, Chun-Hung Lin, Yu-Chia Lai
  • Publication number: 20170201006
    Abstract: A wireless communication circuit and an electronic device are provided. The wireless communication circuit used for an electronic device includes a wireless transceiver unit used to generate a transmitting signal, an impedance matching unit electronically coupled to the wireless transceiver unit, a coupling unit and a system grounding surface. The impedance matching unit includes at least one impedance, the impedance matching unit is used to convert the transmitting signal to a feeding signal according to the impedance value of at least one impedance. The coupling unit is electronically coupled to the impedance matching unit, to radiate the energy of the feeding signal. The system grounding surface is used to transmit a first electromagnetic wave signal via resonance on the plane of the system grounding surface after receiving the energy of the feeding signal.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 13, 2017
    Inventors: Shih-Chia CHIU, Shih-Yuan CHEN, Skye Hui-Hsin WU, Chien-Hao CHIU, Wang-Ta HSIEH, Wei-Hsin SHIH
  • Publication number: 20170179575
    Abstract: A portable electronic device including a front cover, a back cover and a circuit board is provided. The circuit board is located between the front cover and the back cover. The back cover is combined with the front cover and includes a back section, a plurality of side sections and a separator, at least one of the side sections adjacent to the back cover includes a groove close to the back section and a slot far away from the back section, the slot is connected through to the groove, a first antenna unit and a second antenna unit are defined at the side section by the groove and the slot. The separator is located in the groove and the slot.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 22, 2017
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chien-Ming Hsu, Wang-Ta Hsieh, Kuei-Shun Yeh, Shih-Chia Chiu, Chuan-Chien Huang
  • Publication number: 20170005054
    Abstract: The semiconductor device includes a die that contains a substrate and a bond pad. A connective layer is disposed over the die. The connective layer includes a supporting pad and a conductive channel. A portion of the conductive channel passes at least partially through the supporting pad. At least one dielectric region is interposed between the supporting pad and the portion of the conductive channel.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Chien-Chia Chiu, Ming-Yen Chiu
  • Publication number: 20160322337
    Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Shih-Wei Liang, Bor-Rung Su, Chang-Pin Huang, Chien-Chia Chiu, Hsien-Ming Tu, Chun-Hung Lin, Yu-Chia Lai
  • Patent number: D765657
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: September 6, 2016
    Assignee: Dell Products L.P.
    Inventors: Iulius Lucaci, Brian Hargrove Leonard, Sung Kyun Bai, Cheng-Chia Chiu
  • Patent number: D768625
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: October 11, 2016
    Assignee: Dell Products L.P.
    Inventors: Iulius Lucaci, Brian Hargrove Leonard, Cheng-Chia Chiu
  • Patent number: D798859
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 3, 2017
    Assignee: Dell Products L.P.
    Inventors: Joseph E. Jasinski, Brian Hargrove Leonard, Sung Kyun Bai, Cheng-Chia Chiu
  • Patent number: D801965
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 7, 2017
    Assignee: Dell Products L.P.
    Inventors: Joseph E. Jasinski, Brian Hargrove Leonard, Sung Kyun Bai, Cheng-Chia Chiu
  • Patent number: D822020
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 3, 2018
    Assignee: Dell Products L.P.
    Inventors: Antonio T. Latto, Joseph E. Jasinski, Cheng-Chia Chiu, Daniel A. Phipps