Patents by Inventor CHIA-CHUN LIAO

CHIA-CHUN LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12368445
    Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Wen-Yuan Tsai, Chih-Hsien Chang
  • Patent number: 12368543
    Abstract: An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: July 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Chao Chieh Li, Min-Shueh Yuan
  • Patent number: 12361197
    Abstract: A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: July 15, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Fa Zhou, JinXin Liu, Chieh-Fu Chu, Yen-Feng Su, Chia-Chun Liao, Meng-Hsuan Wu, Dei-Pei Liu
  • Publication number: 20250063812
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
  • Publication number: 20250007655
    Abstract: An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, MIN-SHUEH YUAN
  • Patent number: 12166038
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 12153088
    Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Chao Chieh Li, Yu-Tso Lin, Min-Shueh Yuan
  • Publication number: 20240385242
    Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, YU-TSO LIN, MIN-SHUEH YUAN
  • Publication number: 20240378367
    Abstract: A method is provided, including following operations: receiving, by a static voltage drop (SIR) prediction circuitry, floorplan data of a floorplan layout of a semiconductor device; generating a first SIR result by a machine learning model based on the floorplan data; generating a first similarity value based on a comparison of the floorplan data with a plurality of training data; generating a second SIR result based on the first SIR result and a first compensation value, corresponding to the first similarity value, in a mapping table; and generating a bump assignment data to update the floorplan data based on a comparison between the second SIR result with a plurality of predetermined SIR values.
    Type: Application
    Filed: May 30, 2023
    Publication date: November 14, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited
    Inventors: Meng TAI, Chia-Chun LIAO, ShiWen TAN, Song LIU, Cheng JIN
  • Publication number: 20240346225
    Abstract: A method of performing a design rule check includes clustering at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules. The method further includes at least one of transforming at least one of the clustered plurality of operations into a first operation group or a second operation group, or transforming at least one of the clustered plurality of rules into a first rule group or a second rule group. The method even further includes at least one of assigning at least one of the first operation group to a first processor or the second operation group to a second processor, or assigning at least one of the first rule group to the first processor or the second rule group to the second processor.
    Type: Application
    Filed: May 19, 2023
    Publication date: October 17, 2024
    Inventors: Chia-Chun LIAO, Shuang DAI, Yawen CHEN, Meng-Hsuan WU
  • Publication number: 20240305302
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 12, 2024
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Publication number: 20240305301
    Abstract: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: CHAO CHIEH LI, CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHIH-HSIEN CHANG
  • Patent number: 12021537
    Abstract: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Chih-Hsien Chang
  • Patent number: 11996852
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Publication number: 20240164172
    Abstract: Provided is a light-emitting device including a substrate, a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, a blue light absorbing photoresist layer and an atomic layer deposition (ALD) gas barrier layer. The first light-emitting unit includes a first micro LED device and a first light conversion layer wrapping the first micro LED device, the second light-emitting unit includes a second micro LED device and a second light conversion layer wrapping the second micro LED device, and the third light-emitting unit includes a third micro LED device and the third light conversion layer wrapping the third micro LED device. The blue light absorbing photoresist layer covers the first and second light-emitting units, while exposing the third light-emitting unit. The ALD gas barrier layer wraps the first, second, and third light-emitting units, and the blue light absorbing photoresist layer.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 16, 2024
    Applicant: Unique Materials Co., Ltd.
    Inventors: Huan-Wei Tseng, Chun-Wei Chou, Chia-Chun Liao
  • Patent number: 11972186
    Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 30, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Qiuyuan Wu, Shuang Dai, Chia-Chun Liao, Meng-Hsuan Wu
  • Publication number: 20240022255
    Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 18, 2024
    Inventors: Min-Shueh YUAN, Chao-Chieh LI, Chia-Chun LIAO, Yu-Tso LIN, Wen-Yuan TSAI, Chih-Hsien CHANG
  • Publication number: 20230408067
    Abstract: A backlight module and a display apparatus are provided. The backlight module includes a quantum fluorescent film. The quantum fluorescent film includes a light conversion layer. The light conversion layer includes a resin material, a plurality of quantum dots and a plurality of phosphors. The plurality of quantum dots and the plurality of phosphors are dispersed in the resin material.
    Type: Application
    Filed: March 9, 2023
    Publication date: December 21, 2023
    Applicant: Unique Materials Co., Ltd.
    Inventors: Huan-Wei Tseng, Chun-Wei Chou, Chia-Chun Liao
  • Publication number: 20230384373
    Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.
    Type: Application
    Filed: May 30, 2022
    Publication date: November 30, 2023
    Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, YU-TSO LIN, MIN-SHUEH YUAN
  • Publication number: 20230361120
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG