Patents by Inventor CHIA-CHUN LIAO
CHIA-CHUN LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10515964Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: July 30, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10511314Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.Type: GrantFiled: January 24, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
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Publication number: 20190259760Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: ApplicationFiled: April 29, 2019Publication date: August 22, 2019Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
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Patent number: 10276574Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: GrantFiled: July 15, 2016Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
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Patent number: 10270487Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the modulation frequency is higher than a frequency of the reference clock; a reference phase generating unit arranged for generating a reference phase according to the reference clock, the modulation clock, the first FCW, the second FCW, and the third FCW; a digital-controlled oscillator (DCO) arranged for to generating the oscillator clock according to the reference phase. An associated method is also disclosed.Type: GrantFiled: January 26, 2018Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
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Patent number: 10269968Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.Type: GrantFiled: June 3, 2015Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen Chen, Chia-Chun Liao, Chun-Sheng Liang, Shih-Hsun Chang, Jen-Hsiang Lu
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Publication number: 20190068199Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.Type: ApplicationFiled: March 29, 2018Publication date: February 28, 2019Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Robert Bogdan Staszewski
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Publication number: 20190068242Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the modulation frequency is higher than a frequency of the reference clock; a reference phase generating unit arranged for generating a reference phase according to the reference clock, the modulation clock, the first FCW, the second FCW, and the third FCW; a digital-controlled oscillator (DCO) arranged for to generating the oscillator clock according to the reference phase. An associated method is also disclosed.Type: ApplicationFiled: January 26, 2018Publication date: February 28, 2019Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
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Publication number: 20190068201Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.Type: ApplicationFiled: August 21, 2018Publication date: February 28, 2019Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
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Publication number: 20190068206Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.Type: ApplicationFiled: January 24, 2018Publication date: February 28, 2019Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
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Publication number: 20180337181Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Patent number: 10037995Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: November 18, 2016Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20180019242Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
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Patent number: 9768069Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The method includes forming a gate dielectric layer in the first opening and the second opening. The method includes forming a film over the gate dielectric layer. The method includes forming a first work function metal layer in the first opening. The method includes depositing a second work function metal layer in the first opening and the second opening and in direct contact with the first work function metal layer in the first opening and the film in the second opening. A first deposition rate of the second work function metal layer over the first work function metal layer is greater than a second deposition rate of the second work function metal layer over the film.Type: GrantFiled: March 15, 2016Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Chia-Chun Liao, Kuang-Hsin Chen
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Publication number: 20170229461Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: November 18, 2016Publication date: August 10, 2017Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Publication number: 20160359043Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Yi-Jen CHEN, CHIA-CHUN Liao, Chun-Sheng LIANG, Shih-Hsun CHANG, Jen-Hsiang LU
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Patent number: 9484937Abstract: A fractional error correction circuit includes a time-to-digital converter (TDC) configured to detect a phase difference between a reference clock signal and a variable clock signal, and a configurable multiplier coupled with the TDC. The configurable multiplier has a selectable bit size, the selectable bit size being based on a minimum number of bits needed to obtain a reciprocal of a period of the variable clock signal. The TDC is configured to output a fractional error correction value based on the detected phase difference and the reciprocal of the period.Type: GrantFiled: February 17, 2016Date of Patent: November 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chia-Chun Liao
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Patent number: 9419386Abstract: An indication circuit includes a recommended standard 232 (RS232) connector, first to fourth electronic switches, first and second light-emitting diodes (LEDs), and first to fourth resistors. When the RS232 connector outputs a first voltage, the first LED emits, when the RS232 connector outputs a second voltage, the second LED emits.Type: GrantFiled: December 2, 2013Date of Patent: August 16, 2016Assignee: ENNOCONN CORPORATIONInventors: Shih-Chi Liu, Chia-Chun Liao, Cheng-Jen Tseng
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Publication number: 20160197016Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The method includes forming a gate dielectric layer in the first opening and the second opening. The method includes forming a film over the gate dielectric layer. The method includes forming a first work function metal layer in the first opening. The method includes depositing a second work function metal layer in the first opening and the second opening and in direct contact with the first work function metal layer in the first opening and the film in the second opening. A first deposition rate of the second work function metal layer over the first work function metal layer is greater than a second deposition rate of the second work function metal layer over the film.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Shuo HO, Tsung-Yu CHIANG, Chia-Chun LIAO, Kuang-Hsin CHEN
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Publication number: 20160164530Abstract: A fractional error correction circuit includes a time-to-digital converter (TDC) configured to detect a phase difference between a reference clock signal and a variable clock signal, and a configurable multiplier coupled with the TDC. The configurable multiplier has a selectable bit size, the selectable bit size being based on a minimum number of bits needed to obtain a reciprocal of a period of the variable clock signal. The TDC is configured to output a fractional error correction value based on the detected phase difference and the reciprocal of the period.Type: ApplicationFiled: February 17, 2016Publication date: June 9, 2016Inventor: Chia-Chun LIAO