Abstract: A charge pump apparatus including a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit is provided. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit controls the second charge pump system according to the output voltage to adjust the second boost voltage so that the output voltage approaches to a target output value.

Abstract: Organic compounds for target identification, drug discovery, chemical library production, high-throughput screening, fluorophore conjugation, chemiluminescent compound conjugation, creation of proximity induced modulators (e.g., protein degraders)/chimeric molecules, or a combination thereof are described. The compounds can contain small molecule moieties for identification of their potential targets; an isocyanate, photoactivatable groups; chemical moieties for enrichment and detection of target-small molecule moiety interactions; proximity induced modulator element; fluorophores; chemiluminescent groups; or combinations thereof.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.

Abstract: A write voltage generator is connected with a magnetoresistive random access memory. The write voltage generator provides a write voltage during a write operation. A storage state of a selected memory cell in a write path of the magnetoresistive random access memory is changed in response to the write voltage. The write voltage generator includes a temperature compensation circuit and a process corner compensation circuit. The temperature compensation circuit generates a transition voltage according to an ambient temperature. The transition voltage decreases with the increasing ambient temperature. The process corner compensation circuit receives the transition voltage and generates the write voltage.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an mxn array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an mxn array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.

Abstract: A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.

Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: A bandgap reference circuit is applied to the wide range supply voltage. When a power supply voltage is changed, the change amount of the bandgap voltage generated by the bandgap reference circuit is very low. The bandgap reference circuit includes a mirroring circuit, an input circuit and an operation amplifier. The mirroring circuit generates a first current, a second current and a third current to a first node, a second node and an output voltage of the bandgap reference circuit. The input circuit is connected with the first node to receive the first current and connected with the second node to receive the second current. A positive input terminal of the operation amplifier is connected with the first node. A negative input terminal of the operation amplifier is connected with the second node. An output terminal of the operation amplifier is connected with the mirroring circuit.

Abstract: A voltage booster circuit includes a primary charge pump circuit, a secondary charge pump circuit and a transistor. The primary charge pump circuit is used to convert a supply voltage into a boosted voltage in response to a clock signal. The secondary charge pump circuit is used to convert the supply voltage into a regulated voltage in response to the clock signal. The transistor is coupled to the primary charge pump circuit and the secondary charge pump circuit, and has a control terminal receiving the regulated voltage, a first terminal receiving the boosted voltage and a second terminal outputting an output voltage.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A voltage booster circuit includes a primary charge pump circuit, a secondary charge pump circuit and a transistor. The primary charge pump circuit is used to convert a supply voltage into a boosted voltage in response to a clock signal. The secondary charge pump circuit is used to convert the supply voltage into a regulated voltage in response to the clock signal. The transistor is coupled to the primary charge pump circuit and the secondary charge pump circuit, and has a control terminal receiving the regulated voltage, a first terminal receiving the boosted voltage and a second terminal outputting an output voltage.

Abstract: A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.

Abstract: A voltage selection circuit includes a main selection unit, a first re-comparison unit, and a second re-comparison unit. The main selection unit has a first voltage terminal for receiving a first variable voltage, a second voltage terminal for receiving a second variable voltage, and an output terminal for outputting a greater one of the first variable voltage and the second variable voltage as an operation voltage. The first re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the first variable voltage, and the second re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the second variable voltage.

Abstract: A bandgap reference circuit is applied to the wide range supply voltage. When a power supply voltage is changed, the change amount of the bandgap voltage generated by the bandgap reference circuit is very low. The bandgap reference circuit includes a mirroring circuit, an input circuit and an operation amplifier. The mirroring circuit generates a first current, a second current and a third current to a first node, a second node and an output voltage of the bandgap reference circuit. The input circuit is connected with the first node to receive the first current and connected with the second node to receive the second current. A positive input terminal of the operation amplifier is connected with the first node. A negative input terminal of the operation amplifier is connected with the second node. An output terminal of the operation amplifier is connected with the mirroring circuit.

Abstract: A voltage selection circuit includes a main selection unit, a first re-comparison unit, and a second re-comparison unit. The main selection unit has a first voltage terminal for receiving a first variable voltage, a second voltage terminal for receiving a second variable voltage, and an output terminal for outputting a greater one of the first variable voltage and the second variable voltage as an operation voltage. The first re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the first variable voltage, and the second re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the second variable voltage.

Abstract: A power switch circuit includes a voltage selection unit, a first level shift circuit, a second level shift circuit, a first transistor, a second transistor, and a leakage control unit. The voltage selection unit outputs a greater one of a first variable voltage and a system voltage as an operation voltage. The first level shift circuit outputs a first control signal by shifting a voltage of a first input signal. The second level shift circuit outputs a second control signal by shifting a voltage of a second input signal. The first transistor outputs the first variable voltage according to the first control signal. The second transistor outputs the system voltage according to the second control signal. The leakage control unit establishes an electrical connection between first terminal of the first transistor and the control terminal of the second transistor according to the operation voltage.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.