Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.

Abstract: A display panel driving and scanning system includes a timing controller to divide one frame period into first to third time periods. In the first time period, an image processing device calculates an overdriving signal for a current frame based on the current frame and a previous frame. In the second time period, the image processing device outputs the current frame, and a source driver charges the capacitors of the pixels in the liquid crystal display panel based on the current frame. In the third time period, the timing controller drives a backlight driving circuit to turn on a backlight source of the liquid crystal display panel for displaying the current frame.

Abstract: A multiple access communication system in which receiving devices equipped with a method of differentiating signals from multiple users assigned with the same signature, the method comprising steps of determining a plurality of hypothetical signal levels according to a plurality of channel information; obtaining a pre-processed signal according to a received signal received by the receiving device, wherein the pre-processed signal comprises a mixture of a plurality of transmitted signals, and the transmitted signals are generated according to a plurality of signatures and encoded according to a plurality of data signals; calculating a plurality of symbol-level probabilities according to the pre-processed signal and the hypothetical signal levels, wherein the number of signatures may be less than the number of users; obtaining a plurality of log-likelihood ratios, corresponding to the users, and generating a plurality of decoded signals corresponding to the plurality of data signals according to the log-likeli

Abstract: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

Abstract: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

Abstract: A display panel driving and scanning system includes a timing controller to divide one frame period into first to third time periods. In the first time period, an image processing device calculates an overdriving signal for a current frame based on the current frame and a previous frame. In the second time period, the image processing device outputs the current frame, and a source driver charges the capacitors of the pixels in the liquid crystal display panel based on the current frame. In the third time period, the timing controller drives a backlight driving circuit to turn on a backlight source of the liquid crystal display panel for displaying the current frame.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(v)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(y)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A light emitting diode (LED) light source includes a printed circuit board, a heat sink, a plurality of heat conductors, and at least one LED chip. The printed circuit board (PCB) has a plurality of holes. The heat sink connects under the PCB for conducting heat. Each heat conductor is formed on the heat sink corresponding to each hole of the PCB for conducting heat, and each heat conductor has a basin on the topside. The LED chip is attached to the basin of the heat conductor.