Abstract: A method for forming a MOS device with an ultra shallow lightly doped diffusion region includes providing a gate dielectric layer overlying a substrate surface region, forming a gate structure overlying the gate dielectric layer, performing a first implant process using a germanium species to form an amorphous region within an LDD region using the gate structure as a mask, and performing a second implant process in the LDD region using a P-type impurity and a carbon species. A first thermal process activates the P-type impurity in the LDD region, forming side wall spacers overlying the gate structure, and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region adjacent to the gate structure using the gate structure and the spacers as a mask. A second thermal process then activates the first impurity in the active source/drain regions.

Abstract: A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.

Abstract: A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: The image data processing system and method disclosed, processes intermediate compressed binary data representing images scanned for copy or exporting, thereby enabling storage of the copy or export file to a common memory storage device. According to an exemplary embodiment, the image data processing system comprises a binary lossless decompress module, a binary to contone restoration module, and an export processing module, the export processing module processing multiple bit image data for exporting to an image data receiving device.

Abstract: In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.

Abstract: One embodiment is a method for suppressing background inaccuracies in binary to grayscale image conversion. A binary image is converted to a grayscale image using a neighbor map. An image enhancement function is applied to the grayscale image to suppress background inaccuracies in the grayscale image. Another embodiment is method for converting a binary pixel of a binary image to a grayscale pixel of a grayscale image and suppressing noise in the grayscale image using selective filtering of the binary image. Another embodiment is a method for converting a binary image to a first grayscale image and suppressing noise in the first grayscale image to produce a noise suppressed grayscale image using selective filtering of the first grayscale image.

Abstract: A method and system reconstructs a contone image from a binary image by first tagging pixels to identify one of a multiplicity of image content types. The tag information and the pattern of bits surrounding the pixel to be converted to a contone value are used to reconstruct a contone image from a binary image. The pattern of bits in the neighborhood is used to generate a unique identifier. The unique identifier is used as the address for a lookup table with the contone value to be used wherein each lookup table corresponds to an image context type.

Abstract: A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.

Abstract: A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

Abstract: One embodiment is a method for suppressing background inaccuracies in binary to grayscale image conversion. A binary image is converted to a grayscale image using a neighbor map. An image enhancement function is applied to the grayscale image to suppress background inaccuracies in the grayscale image. Another embodiment is method for converting a binary pixel of a binary image to a grayscale pixel of a grayscale image and suppressing noise in the grayscale image using selective filtering of the binary image. Another embodiment is a method for converting a binary image to a first grayscale image and suppressing noise in the first grayscale image to produce a noise suppressed grayscale image using selective filtering of the first grayscale image.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: A method and system reconstructs a contone image from a binary image by first tagging pixels to identify one of a multiplicity of image content types. The tag information and the pattern of bits surrounding the pixel to be converted to a contone value are used to reconstruct a contone image from a binary image. The pattern of bits in the neighborhood is used to generate a unique identifier. The unique identifier is used as the address for a lookup table with the contone value to be used. A filter also generates a contone value. A selector selects between the look-up table contone value and the filter contone value based an image context type.

Abstract: A method and system reconstructs a contone image from a binary image by first tagging pixels to identify one of a multiplicity of image content types. The tag information and the pattern of bits surrounding the pixel to be converted to a contone value are used to reconstruct a contone image from a binary image. The pattern of bits in the neighborhood is used to generate a unique identifier. The unique identifier is used as the address for a lookup table with the contone value to be used wherein each lookup table corresponds to an image context type.

Abstract: A method and system reconstructs a contone image from a binary image by first tagging pixels to identify one of a multiplicity of image content types. The tag information and the pattern of bits surrounding the pixel to be converted to a contone value are used to reconstruct a contone image from a binary image. The pattern of bits in the neighborhood is used to generate a unique identifier. The unique identifier is used as the address for a lookup table with the contone value to be used wherein each lookup table corresponds to an image context type.

Abstract: A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

Abstract: A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

Abstract: A method for forming a MOS device with an ultra shallow lightly doped diffusion region. The method includes providing a semiconductor substrate including a surface region. The method provides a gate dielectric layer overlying the surface region and forms a gate structure overlying a portion of the gate dielectric layer. The method includes performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask. In a specific embodiment, the method includes performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask. The method includes performing a first thermal process to activate the P type impurity in the lightly doped drain region.

Abstract: The image data processing system and method disclosed, processes intermediate compressed binary data representing images scanned for copy or exporting, thereby enabling storage of the copy or export file to a common memory storage device. According to an exemplary embodiment, the image data processing system comprises a binary lossless decompress module, a binary to contone restoration module, and an export processing module, the export processing module processing multiple bit image data for exporting to an image data receiving device.

Abstract: A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.