Patents by Inventor Chia-hao Lee

Chia-hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748339
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereon; a first well region disposed in a portion of the semiconductor layer; a second well region disposed in another portion of the semiconductor layer; a pair of third well regions disposed in a portion of the semiconductor layer at opposite sides of the second well region; a plurality of isolation elements disposed over the semiconductor layer, respectively between the third well regions and the first and second well region; a deep well region disposed in a portion of the semiconductor substrate adjacent to the semiconductor layer between the first and second well region; a first doping region disposed in the first well region; and second doping regions disposed in the third well regions.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 29, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9697806
    Abstract: A self-refresh control method for a display system includes receiving a frame from a video source of the display system; storing the frame in a storage module of the display system according to a writing timing sequence signal; accessing data stored in the storage module as a self-refresh frame according to a reading timing sequence, for outputting the self-refresh frame to a display device of the display system; and adjusting the reading timing sequence signal according to the writing timing sequence signal and the reading timing sequence signal.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 4, 2017
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chia-Hao Lee, Yu-Hsuan Huang, Chueh-An Tsai
  • Publication number: 20170162691
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Sing-Lin WU, Chung-Hsuan WANG, Yung-Lung CHOU, Chia-Hao LEE, Chih-Cherng LIAO
  • Patent number: 9666699
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 30, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jun-Wei Chen
  • Patent number: 9646964
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 9, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Pei-Heng Hung, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Publication number: 20170117408
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung LIN, Chia-Hao LEE, Chih-Cherng LIAO
  • Patent number: 9614078
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: April 4, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee, Chih-Cherng Liao
  • Publication number: 20170077091
    Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 16, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Jun-Wei CHEN
  • Publication number: 20170025411
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Pei-Heng HUNG, Hsiung-Shih CHANG, Chia-Hao LEE, Jui-Chun CHANG
  • Patent number: 9553091
    Abstract: A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Ching-Yi Hsu, Jun-Wei Chen
  • Patent number: 9548354
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Po-Heng Lin, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9548375
    Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
  • Patent number: 9530900
    Abstract: A Schottky diode is provided, which includes a well of a first conductive type and a lightly doped region of a second conductive type on the well, wherein the first conductive type is opposite to the second conductive type. The Schottky diode includes a heavily doped region of the second conductive type on the well, and a gate structure on a part of the lightly doped region. The gate structure includes a gate electrode and a gate dielectric layer. The lightly doped region not covered by the gate structure and the heavily doped region are disposed at two opposite sides of the gate structure, respectively. The Schottky diode includes a first contact electrically connecting the heavily doped region and a first electrode, a second contact electrically connecting the gate electrode and a second electrode, and a third contact electrically connecting the lightly doped region and the second electrode.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: December 27, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9525045
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate having a first conductive type and an epitaxial layer having the first conductive type disposed over the substrate, wherein a trench is formed in the epitaxial layer. The semiconductor device also includes a polysilicon layer having the first conductive type disposed in the trench. The semiconductor device further includes a doped region having a second conductive type disposed along a sidewall and a bottom of the trench in the epitaxial layer, wherein a thickness along the sidewall and the bottom of the trench is uniform, and wherein the thickness is a vertical distance between the outermost side of the trench to the sidewall or the bottom of the trench.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 20, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chia-Hao Lee, Pei-Heng Hung, Chih-Cherng Liao, Jun-Wei Chen
  • Publication number: 20160359040
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj KUMAR, Tsung-Hsiung LEE, Pei-Heng HUNG, Chia-Hao LEE, Jui-Chun CHANG
  • Patent number: 9502584
    Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 22, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
  • Patent number: 9478644
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well region having the first conduction type is disposed in the semiconductor layer. A second well and a third well having a second conduction type are disposed to opposite sides of the first well region. The second well and the third well are separated from the first well region. A first anode doped region is disposed in the second well. A second anode doped region and a third anode doped region having the first conduction type are disposed in the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9466730
    Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 11, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
  • Publication number: 20160239329
    Abstract: A method for live migrating a virtual machine includes connecting to a virtual machine operated in a first host by a client; transmitting condition data of the virtual machine to a second host by the first host during a transmitting time, the first host and the second host being located at different net domains; transmitting a variance of condition data of the virtual machine generated in the transmitting time to the second host by the first host; providing a notification to the client to reconnect to the second host by the first host; modifying a network packets transmitting rule by the client based on the notification of the first host, and activating the virtual machine by the second host based on the condition data of the virtual machine and the variance of the condition data of the virtual machine thereby maintaining the connection between the client and the virtual machine.
    Type: Application
    Filed: June 9, 2015
    Publication date: August 18, 2016
    Inventors: Fu-Hau HSU, Tzung-Ting LIN, Wei-Tai CAI, Chia-Hao LEE
  • Patent number: 9318601
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 19, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Pei-Heng Hung, Priyono Tri Sulistyanto, Chia-Hao Lee, Chih-Cherng Liao, Shang-Hui Tu