Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.

Abstract: The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.

Abstract: A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

Abstract: A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode which penetrate through the protection layer and are disposed on the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.

Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, and an aluminum gallium nitride layer disposed on the first gallium nitride layer. The semiconductor device also includes an upper recess and a lower recess disposed in the aluminum gallium nitride layer, wherein the upper recess adjoins the lower recess, and the upper recess has a width that is greater than that of the lower recess. The semiconductor device further includes a second gallium nitride layer disposed in the first recess and the second recess, and a gate structure disposed on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.

Abstract: A flash memory is provided. The flash memory includes a semiconductor substrate, a floating gate structure on the semiconductor substrate, an inter-gate dielectric layer covering sidewalls and a top surface of the floating gate structure, and a control gate on the inter-gate dielectric layer. The floating gate structure includes a floating gate dielectric layer on the semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have sloped sidewalls that face each other, and a floating gate on the floating gate dielectric layer and between the pair of dielectric spacers. The floating gate has a pair of tips over the respective sloped sidewalls of the pair of dielectric spacers.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer disposed over the substrate, and a first epitaxial layer disposed over the oxide layer. The first epitaxial layer has the first conductivity type. The semiconductor device also includes a second epitaxial layer disposed over the first epitaxial layer and a third epitaxial layer disposed over the second epitaxial layer. The second epitaxial layer has a second conductivity type that is opposite to the first conductivity type. The third epitaxial layer has the first conductivity type.

Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

Abstract: The present invention discloses a conjugated polymer, which is a random copolymer, and with Formula I: Additionally, the present invention also discloses an organic photovoltaic device comprising the conjugated polymer.

Abstract: A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first oxide layer disposed over the substrate, a second oxide layer, and a semiconductor layer disposed over the second oxide layer. The second oxide layer is disposed at one side of the first oxide layer and is in contact with the first oxide layer. The second oxide layer partially overlaps the first oxide layer, and the first oxide layer and the second oxide layer include the same oxide.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first oxide layer disposed over the substrate, a second oxide layer, and a semiconductor layer disposed over the second oxide layer. The second oxide layer is disposed at one side of the first oxide layer and is in contact with the first oxide layer. The second oxide layer partially overlaps the first oxide layer, and the first oxide layer and the second oxide layer include the same oxide.

Abstract: A semiconductor device includes an epitaxial layer disposed over a semiconductor substrate, a drift region disposed in the epitaxial layer and adjacent to an upper surface of the epitaxial layer, a gate structure disposed over the epitaxial layer, a source region disposed in the epitaxial layer outside the drift region, and a drain region disposed in the drift region. The epitaxial layer and the drift region have a first conductivity type. The semiconductor device also includes a plurality of doped region pairs disposed in the drift region and arranged in a direction from the drain region toward the source region. Each of the plurality of doped region pairs includes a first doped region having a second conductivity type opposite to the first conductivity type, and a second doped region disposed over the first doped region. The second doped region has the first conductivity type.

Abstract: A semiconductor device includes an epitaxial layer disposed over a semiconductor substrate, a drift region disposed in the epitaxial layer and adjacent to an upper surface of the epitaxial layer, a gate structure disposed over the epitaxial layer, a source region disposed in the epitaxial layer outside the drift region, and a drain region disposed in the drift region. The epitaxial layer and the drift region have a first conductivity type. The semiconductor device also includes a plurality of doped region pairs disposed in the drift region and arranged in a direction from the drain region toward the source region. Each of the plurality of doped region pairs includes a first doped region having a second conductivity type opposite to the first conductivity type, and a second doped region disposed over the first doped region. The second doped region has the first conductivity type.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer disposed over the substrate, and a first epitaxial layer disposed over the oxide layer. The first epitaxial layer has the first conductivity type. The semiconductor device also includes a second epitaxial layer disposed over the first epitaxial layer and a third epitaxial layer disposed over the second epitaxial layer. The second epitaxial layer has a second conductivity type that is opposite to the first conductivity type. The third epitaxial layer has the first conductivity type.

Abstract: A method for manufacturing a high-voltage semiconductor device is provided. The method includes providing a substrate having a first conductive type. The method also includes performing a first ion implantation process so that a first doped region is formed in the substrate. The first doped region has a second conductive type that is different from the first conductive type. The method further includes forming a first epitaxial layer over the substrate. In addition, the method includes performing a second ion implantation process so that a second doped region is formed in the first epitaxial layer. The second doped region has the second conductive type, and the first doped region is in direct contact with the second doped region.

Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.