Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures surrounded by the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features, and the reinforced plate is thinner than the redistribution structure. A thickness ratio of a first thickness of the reinforced plate to a second thickness of the redistribution structure is greater than about 0.5. The package structure further includes one or more chip structures bonded to the redistribution structure.

Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

Abstract: An embodiment interposer includes a first electrically conducting line structure, an electrically conducting via structure that is electrically connected to the first electrically conducting line structure, and a second electrically conducting line structure formed along with the electrically conducting via structure as a monolithic structure. In some embodiments, a portion of the first electrically conducting line structure may be provided within the electrically conducting via structure such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure such that the first electrically conducting line structure and the electrically conducting via structure share a common surface. In other embodiments, the interposer may further include a via land structure electrically connected to the first electrically conducting line structure.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

Abstract: A method includes forming a redistribution structure, wherein forming the redistribution structure includes forming a first conductive material on a portion of a first seed layer, forming a mask over the first seed layer and the first conductive material, wherein an opening in the mask at least partially exposes the first conductive material, forming a first conductive via in the opening, etching portions of the first seed layer using the first conductive material as an etching mask, depositing a first insulating layer over the first conductive via, the first conductive material and remaining portions of the first seed layer, and etching the first insulating layer such that a portion of the first conductive via protrudes above a top surface of the first insulating layer, and attaching a first die to the redistribution structure using first electrical connectors.

Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch, a discharging circuit and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The discharging circuit is selectively coupled to the power output terminal, and arranged to discharge a battery cell of the battery pack when being coupled to the power output terminal. The control unit is coupled to the charge control switch and the discharging circuit, and determines whether to turn off the charge control switch and control the discharging circuit to couple to the power output terminal according to at least an over-voltage detection based on a signal based on the connection terminal.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.