Patents by Inventor Chia-Hsiang Lin

Chia-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286744
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 10665473
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Publication number: 20200075569
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Feng-Cheng HSU, Chia-Hsiang LIN
  • Publication number: 20190139784
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 9973075
    Abstract: A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 15, 2018
    Assignee: MediaTek Inc.
    Inventors: Nien-Hui Kung, Kuo-Chang Lo, Chia-Hsiang Lin
  • Publication number: 20170288427
    Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The control unit is coupled to the charge control switch and the connection terminal, and determines whether to turn off the charge control switch according to a signal based on the connection terminal, wherein the signal based on the connection terminal indicates at least one of an over-voltage condition and an over-temperature condition.
    Type: Application
    Filed: June 3, 2016
    Publication date: October 5, 2017
    Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
  • Patent number: 9583365
    Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu
  • Publication number: 20170025944
    Abstract: A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.
    Type: Application
    Filed: January 27, 2016
    Publication date: January 26, 2017
    Inventors: Nien-Hui Kung, Kuo-Chang Lo, Chia-Hsiang Lin
  • Patent number: 8917062
    Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: December 23, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
  • Publication number: 20140062435
    Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
  • Publication number: 20130313121
    Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu
  • Patent number: 8563231
    Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung
  • Publication number: 20130075364
    Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung
  • Publication number: 20120249085
    Abstract: An exemplary method for controlling a charging current is adapted to a charging device. The charging device receives an input voltage to thereby output the charging current. The method includes the following steps of: making the charging current have a first value; judging whether the input voltage is less than a preset reference voltage; and if the input voltage is judged to be less than the preset reference voltage, decreasing the charging current from the first value step by step until the input voltage retrieves back above the preset reference voltage.
    Type: Application
    Filed: July 13, 2011
    Publication date: October 4, 2012
    Applicant: RICHTEK TECHNOLOGY CORP
    Inventors: Chia-Hsiang Lin, Li-Wei Lee, Chen-Hsiang Hsiao, Hsuan-Kai Wang
  • Publication number: 20120169294
    Abstract: A circuit and method for power path management track the input voltage at a power input terminal to generate a reference voltage, and generate a control signal for controlling a charger control circuit coupled between a power output terminal and a charger output terminal according to the difference between the voltage at the power output terminal and the reference voltage.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Applicant: Richtek Technology Corp.
    Inventors: Hsuan-Kai WANG, Nien-Hui KUNG, Chia-Hsiang LIN
  • Patent number: 8132503
    Abstract: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 13, 2012
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Kuei-Shun Chen, Chin-Hsiang Lin, T. H. Lin, Chia-Hsiang Lin
  • Patent number: 8119992
    Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
  • Publication number: 20100127670
    Abstract: A charger including a regulator, a controller and a compensation-adjusting unit for accurately charging to a battery device is provided. The regulator provides a charging current to the battery device. The controller is coupled to the regulator for controlling the charging current. The compensation-adjusting unit is coupled to the regulator and the battery device for receiving a first reference voltage. In a first operation mode, the compensation-adjusting unit outputs the first reference voltage to the regulator. In a second operation mode, the controller instructs the regulator to transiently generate a first charging current and a second charging current. Responsive to the first and the second charging currents, the output voltage of the battery device presents a first output voltage and a second output voltage. The compensation-adjusting unit pre-estimates a parasitic resistance of the battery device by detecting the first and the second output voltage, thus compensating the first reference voltage.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Ke-Horng Chen, Hong-Wei Huang, Chia-Hsiang Lin, Hsing-Yi Chen
  • Publication number: 20090294685
    Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.
    Type: Application
    Filed: August 7, 2009
    Publication date: December 3, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
  • Patent number: 7582538
    Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: September 1, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen