Patents by Inventor Chia-Hsiang Lin

Chia-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238407
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Patent number: 11397302
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: July 26, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20220212227
    Abstract: A method for manufacturing a golf ball having a non-uniform dot pattern is provided. Firstly, a semi-finished product of a golf ball is provided, which includes a ball body and a base layer covering an outer surface of the ball body. After that, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball in a spraying manner from each of an upper position and a lower position.
    Type: Application
    Filed: June 30, 2021
    Publication date: July 7, 2022
    Inventors: CHIA-SHENG HUANG, CHI-LING LIN, CHIA-CHENG WU, CHING-HSIANG LIU
  • Publication number: 20220212219
    Abstract: An apparatus for manufacturing golf balls each having an exterior pattern includes a conveying device and a spraying device. The spraying device is disposed at one side of a first processing area. The conveying device is configured to convey a ball-shaped body into the first processing area along a predetermined path, and to rotate the ball-shaped body at a predetermined speed. The spraying device includes a first sprayer and a second sprayer. The first sprayer and the second sprayer are configured to apply a color paint to the ball-shaped body from each of an upper position and a lower position.
    Type: Application
    Filed: August 6, 2021
    Publication date: July 7, 2022
    Inventors: CHIA-SHENG HUANG, CHI-LING LIN, CHIA-CHENG WU, CHING-HSIANG LIU
  • Publication number: 20220208684
    Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Ting-Chin Cho, Igor Elkanovich, Amnon Parnass, Chia-Hsiang Chang, Tsai-Ming Yang, Yen-Chung T. Chen, Ting-Hsu Chien, Yuan-Hung Lin, Chao-Ching Huang, Li-Ya Tseng, Pei Yu, Jia-Liang Chen, Yen-Wei Chen, Chung-Kai Wang, Chun-Hsu Chen, Yu-Ju Chang, Li-Hua Lin, Zanyu Yang
  • Publication number: 20220205128
    Abstract: Provides an electropolishing treatment method for a stainless steel workpiece, wherein the method comprises the following steps: placing the stainless steel workpiece in an oxalic acid solution and performing supersonic oscillation; performing a first electropolishing treatment to the stainless steel workpiece, wherein the first electropolishing treatment uses the stainless steel workpiece as an anode and 10% to 15% perchloric acid as an electrolyte, and when a constant voltage is set as 12V, the first electropolishing treatment procedure is performed; and performing a second electropolishing treatment to the stainless steel workpiece, wherein the second electropolishing treatment uses the stainless steel workpiece after the first electropolishing treatment as an anode, and an electrolyte consists of ethanol, sulfuric acid and perchloric acid, and when a constant voltage is set as 12V, the second electropolishing treatment is performed to obtain the stainless steel workpiece after the second electropolishing
    Type: Application
    Filed: December 27, 2021
    Publication date: June 30, 2022
    Inventors: CHUN-HSIANG KAO, YI-CHERNG FERNG, KUO-KUANG JEN, SHUN-YI JIAN, MING-HSIEN LIN, YU-CHIH TZENG, CHIA-YU LEE
  • Patent number: 11251142
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Publication number: 20220045016
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.
    Type: Application
    Filed: October 15, 2020
    Publication date: February 10, 2022
    Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Chia-Hsiang LIN
  • Publication number: 20220020693
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.
    Type: Application
    Filed: December 18, 2020
    Publication date: January 20, 2022
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
  • Publication number: 20220020700
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
    Type: Application
    Filed: December 18, 2020
    Publication date: January 20, 2022
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
  • Publication number: 20210305821
    Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch, a discharging circuit and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The discharging circuit is selectively coupled to the power output terminal, and arranged to discharge a battery cell of the battery pack when being coupled to the power output terminal. The control unit is coupled to the charge control switch and the discharging circuit, and determines whether to turn off the charge control switch and control the discharging circuit to couple to the power output terminal according to at least an over-voltage detection based on a signal based on the connection terminal.
    Type: Application
    Filed: April 26, 2021
    Publication date: September 30, 2021
    Applicant: Media Tek Inc.
    Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
  • Patent number: 11107801
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Chia-Hsiang Lin
  • Patent number: 11038358
    Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The control unit is coupled to the charge control switch and the connection terminal, and determines whether to turn off the charge control switch according to a signal based on the connection terminal, wherein the signal based on the connection terminal indicates at least one of an over-voltage condition and an over-temperature condition.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 15, 2021
    Assignee: MediaTek Inc.
    Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
  • Publication number: 20200286744
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 10665473
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Publication number: 20200075569
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Feng-Cheng HSU, Chia-Hsiang LIN
  • Publication number: 20190139784
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 9973075
    Abstract: A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 15, 2018
    Assignee: MediaTek Inc.
    Inventors: Nien-Hui Kung, Kuo-Chang Lo, Chia-Hsiang Lin
  • Publication number: 20170288427
    Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The control unit is coupled to the charge control switch and the connection terminal, and determines whether to turn off the charge control switch according to a signal based on the connection terminal, wherein the signal based on the connection terminal indicates at least one of an over-voltage condition and an over-temperature condition.
    Type: Application
    Filed: June 3, 2016
    Publication date: October 5, 2017
    Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
  • Patent number: 9583365
    Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu