Patents by Inventor Chia-Hsiang Lin
Chia-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11605600Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.Type: GrantFiled: October 15, 2020Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Puu Jeng, Po-Yao Lin, Shuo-Mao Chen, Chia-Hsiang Lin
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Publication number: 20220384313Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Patent number: 11251142Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.Type: GrantFiled: May 22, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
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Publication number: 20220045016Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.Type: ApplicationFiled: October 15, 2020Publication date: February 10, 2022Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Chia-Hsiang LIN
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Publication number: 20220020700Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.Type: ApplicationFiled: December 18, 2020Publication date: January 20, 2022Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Publication number: 20220020693Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.Type: ApplicationFiled: December 18, 2020Publication date: January 20, 2022Inventors: Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Publication number: 20210305821Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch, a discharging circuit and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The discharging circuit is selectively coupled to the power output terminal, and arranged to discharge a battery cell of the battery pack when being coupled to the power output terminal. The control unit is coupled to the charge control switch and the discharging circuit, and determines whether to turn off the charge control switch and control the discharging circuit to couple to the power output terminal according to at least an over-voltage detection based on a signal based on the connection terminal.Type: ApplicationFiled: April 26, 2021Publication date: September 30, 2021Applicant: Media Tek Inc.Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
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Patent number: 11107801Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.Type: GrantFiled: December 27, 2018Date of Patent: August 31, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Puu Jeng, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Chia-Hsiang Lin
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Patent number: 11038358Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The control unit is coupled to the charge control switch and the connection terminal, and determines whether to turn off the charge control switch according to a signal based on the connection terminal, wherein the signal based on the connection terminal indicates at least one of an over-voltage condition and an over-temperature condition.Type: GrantFiled: June 3, 2016Date of Patent: June 15, 2021Assignee: MediaTek Inc.Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
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Publication number: 20200286744Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
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Patent number: 10665473Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.Type: GrantFiled: November 8, 2017Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
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Publication number: 20200075569Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.Type: ApplicationFiled: December 27, 2018Publication date: March 5, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Feng-Cheng HSU, Chia-Hsiang LIN
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Publication number: 20190139784Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
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Patent number: 9973075Abstract: A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.Type: GrantFiled: January 27, 2016Date of Patent: May 15, 2018Assignee: MediaTek Inc.Inventors: Nien-Hui Kung, Kuo-Chang Lo, Chia-Hsiang Lin
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Publication number: 20170288427Abstract: A charger circuit for use in controlling charge of a battery pack, which includes a charge control switch and a control unit. The charger circuit has at least one power output terminal and one connection terminal for coupling the battery pack. The charge control switch is arranged to selectively provide a power from a power source to the battery pack through the power output terminal. The control unit is coupled to the charge control switch and the connection terminal, and determines whether to turn off the charge control switch according to a signal based on the connection terminal, wherein the signal based on the connection terminal indicates at least one of an over-voltage condition and an over-temperature condition.Type: ApplicationFiled: June 3, 2016Publication date: October 5, 2017Inventors: Kuo-Chang Lo, Chia-Hsiang Lin, Chih-Chien Huang
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Patent number: 9583365Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.Type: GrantFiled: May 25, 2012Date of Patent: February 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu
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Publication number: 20170025944Abstract: A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.Type: ApplicationFiled: January 27, 2016Publication date: January 26, 2017Inventors: Nien-Hui Kung, Kuo-Chang Lo, Chia-Hsiang Lin
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Patent number: 8917062Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.Type: GrantFiled: August 29, 2012Date of Patent: December 23, 2014Assignee: Richtek Technology CorporationInventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
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Publication number: 20140062435Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
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Publication number: 20130313121Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu