Patents by Inventor Chia-Hsiang Lin

Chia-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130313121
    Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hui Yu, Kuo-Chung Yee, Chen-Hua Yu, Yeong-Jyh Lin, Chia-Hsiang Lin, Liang-Ju Yen, Lawrence Chiang Sheu
  • Patent number: 8563231
    Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung
  • Publication number: 20130075364
    Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung
  • Publication number: 20120249085
    Abstract: An exemplary method for controlling a charging current is adapted to a charging device. The charging device receives an input voltage to thereby output the charging current. The method includes the following steps of: making the charging current have a first value; judging whether the input voltage is less than a preset reference voltage; and if the input voltage is judged to be less than the preset reference voltage, decreasing the charging current from the first value step by step until the input voltage retrieves back above the preset reference voltage.
    Type: Application
    Filed: July 13, 2011
    Publication date: October 4, 2012
    Applicant: RICHTEK TECHNOLOGY CORP
    Inventors: Chia-Hsiang Lin, Li-Wei Lee, Chen-Hsiang Hsiao, Hsuan-Kai Wang
  • Publication number: 20120169294
    Abstract: A circuit and method for power path management track the input voltage at a power input terminal to generate a reference voltage, and generate a control signal for controlling a charger control circuit coupled between a power output terminal and a charger output terminal according to the difference between the voltage at the power output terminal and the reference voltage.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Applicant: Richtek Technology Corp.
    Inventors: Hsuan-Kai WANG, Nien-Hui KUNG, Chia-Hsiang LIN
  • Patent number: 8132503
    Abstract: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 13, 2012
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Kuei-Shun Chen, Chin-Hsiang Lin, T. H. Lin, Chia-Hsiang Lin
  • Patent number: 8119992
    Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
  • Publication number: 20100127670
    Abstract: A charger including a regulator, a controller and a compensation-adjusting unit for accurately charging to a battery device is provided. The regulator provides a charging current to the battery device. The controller is coupled to the regulator for controlling the charging current. The compensation-adjusting unit is coupled to the regulator and the battery device for receiving a first reference voltage. In a first operation mode, the compensation-adjusting unit outputs the first reference voltage to the regulator. In a second operation mode, the controller instructs the regulator to transiently generate a first charging current and a second charging current. Responsive to the first and the second charging currents, the output voltage of the battery device presents a first output voltage and a second output voltage. The compensation-adjusting unit pre-estimates a parasitic resistance of the battery device by detecting the first and the second output voltage, thus compensating the first reference voltage.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Ke-Horng Chen, Hong-Wei Huang, Chia-Hsiang Lin, Hsing-Yi Chen
  • Publication number: 20090294685
    Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.
    Type: Application
    Filed: August 7, 2009
    Publication date: December 3, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
  • Patent number: 7582538
    Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: September 1, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
  • Patent number: 7480865
    Abstract: An auxiliary operation interface of a digital recording/reproducing apparatus includes a targeting item, a switching button set and an audio prompt generator. The targeting item is optionally triggered to have the digital recording/reproducing apparatus execute a selected function. The audio prompt generator is enabled to generate an audio prompt when the targeting item is triggered. The audio prompt generator is optionally enabled or disabled by an operation of the switching button set.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: January 20, 2009
    Assignee: Lite-On It Corp.
    Inventor: Chia-Hsiang Lin
  • Publication number: 20080060534
    Abstract: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 13, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Shun Chen, Chin-Hsiang Lin, T.H. Lin, Chia-Hsiang Lin
  • Patent number: 7226873
    Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: June 5, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Sung Yen, Kuei-Shun Chen, Chia-Hsiang Lin, Lawrence Lin, Tsung Hsien Lin
  • Publication number: 20060228816
    Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Chen
  • Publication number: 20060211237
    Abstract: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.
    Type: Application
    Filed: March 21, 2005
    Publication date: September 21, 2006
    Inventors: Kuei-Shun Chen, Chin-Hsiang Lin, T. Lin, Chia-Hsiang Lin
  • Publication number: 20060110941
    Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.
    Type: Application
    Filed: November 22, 2004
    Publication date: May 25, 2006
    Inventors: Yung-Sung Yen, Kuei-Shun Chen, Chia-Hsiang Lin, Lawrence Lin, T. Lin
  • Publication number: 20060088288
    Abstract: An auxiliary operation interface includes a guiding menu and an audio prompt generator. The guiding menu has a targeting item optionally triggered to have the digital recording/reproducing apparatus execute a selected function. The audio prompt generator is enabled to generate a first audio prompt when the targeting item is triggered to enter a first function and generate a second audio prompt when the targeting item is triggered to enter a second function.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Inventor: Chia-Hsiang Lin
  • Publication number: 20060088280
    Abstract: A remote controller includes at least a button and an audio prompt generator is disclosed. The button is used for cooperating with a digital recording/reproducing apparatus. The audio prompt generator generates an audio prompt in response to a triggering operation done on the button.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Inventor: Chia-Hsiang Lin
  • Publication number: 20060087938
    Abstract: An auxiliary operation interface of a digital recording/reproducing apparatus includes a targeting item, a switching button set and an audio prompt generator. The targeting item is optionally triggered to have the digital recording/reproducing apparatus execute a selected function. The audio prompt generator is enabled to generate an audio prompt when the targeting item is triggered. The audio prompt generator is optionally enabled or disabled by an operation of the switching button set.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Inventor: Chia-Hsiang Lin
  • Publication number: 20060059488
    Abstract: A task confirmation method is used in a task executing apparatus. A scheduled task is going to be executed by the task executing apparatus at a preset time point. After the scheduling operation, whether conditions of the task executing apparatus are ready for executing the scheduled task at the preset time point are checked in response to a power-off signal of the task executing apparatus and/or an awaking signal for waking up the powered-off task executing apparatus. If the conditions of the task executing apparatus are not ready for executing the scheduled task at the preset time point, a warning message will be outputted.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 16, 2006
    Inventor: Chia-Hsiang Lin