Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: Provided are an LCP film and a laminate comprising the same. The LCP film is made of an LCP resin comprising a structural unit represented by Formula (1): -L1-Ar-L2- (1), wherein -L1- and -L2- are respectively —O— or —CO—; —Ar— is an arylene group. Formula (1) comprises structural units Based on a total molar number of the structural unit represented by Formula (1), a molar number of the structural unit represented by Formula (I) is in the range from 15 mole % to mole %, and a sum of molar numbers of the structural units represented by Formulae (I) and (II) is in the range from 80 mole % to 100 mole %. The LCP film has a thickness and a transmittance, wherein when values of the thickness (in ?m) and the transmittance are put into Formula (III), the obtained value is from 0.055 to 0.090. Formula (III): Log(1/TT %)/(Thickness)0.5.

Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.

Abstract: An example apparatus determines a size of a dirty region of a video frame; after the size of the dirty region satisfies a threshold: encode the dirty region of the video frame to generate an encoded dirty region; and cause storing of the dirty region in the cache; and after the size of the dirty region does not satisfy the threshold: cause storing of the video frame in a volatile memory that is separate from the cache; and encode the video frame via inter-encoding to generate an encoded video frame.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: An electronic device includes a base, a multi-stage sensor, a top cover, and a side cover. The multi-stage sensor is configured to sense a sensed area. The top cover includes a top-sensed element, and the top cover is detachably connected to a top side of the base, so that the top-sensed element can be selectively in or not in the sensed area. The side cover includes a side-sensed element, and the side cover is detachably adjacent to a front side of the base, so that the side-sensed element can be selectively in or not in the sensed area. In response to that only the top-sensed element is in the sensed area, the multi-stage sensor outputs a first signal. In response to that neither the top-sensed element nor the side-sensed element is in the sensed area, the multi-stage sensor outputs a second signal.

Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: A method, a communication apparatus using the method, and a base station apparatus are disclosed. The method includes arranging user equipment to receive a downlink control channel signal associated with a physical downlink control channel; and configuring the user equipment to monitor the physical downlink control channel for control-resource set information. The control-resource set information corresponds to time and frequency resource allocation information related to the physical downlink control channel. The control-resource set information includes at least one parameter.

Abstract: A security lock has a fixing element and at least one hook. The fixing element is mounted in a security slot of an electronic device. The hook is capable of moving axially with respect to the fixing element, and the hook moves radially outward along a guiding structure of the fixing element to engage with the security slot, the fixing element stays static, i.e., without moving and rotating as the hook is moving. Therefore, the security lock won't press the security slot, and further prevents damage to the security slot caused by frequently or constantly loaded with the security lock. Furthermore, without moving and rotating in a mounting process of the security lock, the fixing element holds the hook to steadily engage with the security slot, and thus an overall anti-pulling and anti-pushing performances are enhanced.

Abstract: A monitoring system and a monitoring method of network latency are provided. The monitoring method includes: making a server communicatively connect to a first host and a second host, wherein the first host provides a first virtual machine operating a first application and the second host provides a second virtual machine operating a second application; and calculating, by the server, time latency information associated with a communication between the first application and the second application according to data obtained from the first host and the second host, and displaying the time latency information through a visual interface, wherein the time latency information includes a total latency of the communication between the first application and the second application.

Abstract: A display includes an outer frame, a supporting frame, a display module, and a covering member. The supporting frame is accommodated in the outer frame. The display module is disposed on a supporting member of the supporting frame. The supporting member extends toward a display region of the display module from the supporting frame. On a first surface of the display module, a projection area of the supporting member and a projection area of an first optical film of the display module are partially overlapped with each other. A third surface of the covering member is closely attached to a second optical film of the display module. The covering member has an extension portion. The extension portion extends from a fourth surface opposite to the third surface toward a direction away from the third surface, and the extension portion is coplanar with the outer side surface of the outer frame.