Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate.

Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.

Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and where the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.

Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.

Abstract: A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate.

Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.

Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.

Abstract: A method for cleaning an etching chamber is disclosed. The method comprises providing an etching chamber; introducing a first gas comprising an inert gas into the etching chamber for a first period of time; and transporting a first wafer into the etching chamber after the first period of time, wherein the first wafer undergoes an etching process.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.

Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.

Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.

Abstract: A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

Abstract: A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess.