Patents by Inventor Chia-Jen Chen

Chia-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lithography mask
    Patent number: 9995999
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • LITHOGRAPHY MASK WITH BOTH TRANSMISSION-TYPE AND REFLECTIVE-TYPE OVERLAY MARKS AND METHOD OF FABRICATING THE SAME
    Publication number: 20180149959
    Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 31, 2018
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
  • Method of forming gate structure of a semiconductor device
    Patent number: 9978853
    Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process
    Patent number: 9960160
    Abstract: The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • FinFET Device
    Publication number: 20180090607
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Composite dummy gate with conformal polysilicon layer for FinFET device
    Patent number: 9923079
    Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Ryan Chia-Jen Chen, Ming-Ching Chang, Tzu-Yen Hsieh
  • Metal gate isolation structure and method forming same
    Patent number: 9917085
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Simultaneous formation of source/drain openings with different profiles
    Patent number: 9870954
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof
    Patent number: 9869928
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chih-Tsung Shih, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Metal Gate Isolation Structure and Method Forming Same
    Publication number: 20170345820
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 30, 2017
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • FinFET device
    Patent number: 9825173
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Methods for Forming Fin Field-Effect Transistors
    Publication number: 20170229348
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Process of manufacturing Fin-FET device
    Patent number: 9704974
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, An-Shen Chang, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chia-Tai Lin, Chih-Tang Peng
  • Semiconductor fin structures and methods for forming the same
    Patent number: 9698055
    Abstract: A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Ryan Chia-Jen Chen, Srisuda Thitinun
  • METHOD OF FORMING GATE STRUCTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20170186853
    Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
  • Method of fabricating a semiconductor device including a plurality of isolation features
    Patent number: 9685344
    Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu Chao Lin, Chih-Tang Peng, Shun-Hui Yang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Method of making an extreme ultraviolet pellicle
    Patent number: 9664999
    Abstract: The present disclosure relates to an extreme ultraviolet (EUV) pellicle having a pellicle film connected to a pellicle frame. In some embodiments, the EUV pellicle has a substrate, and an adhesive material disposed onto the substrate. A pellicle frame is connected to the substrate by way of the adhesive material. The pellicle frame is configured to mount the substrate to an extreme ultraviolet (EUV) reticle.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Mask and method for forming the same
    Patent number: 9651857
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Ta-Cheng Lien, Anthony Yen
  • Semiconductor fin structures and methods for forming the same
    Patent number: 9633905
    Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Integrated high-K/metal gate in CMOS process flow
    Patent number: 9601388
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor