Patents by Inventor Chia-Jen Chen

Chia-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making an extreme ultraviolet pellicle
    Patent number: 9664999
    Abstract: The present disclosure relates to an extreme ultraviolet (EUV) pellicle having a pellicle film connected to a pellicle frame. In some embodiments, the EUV pellicle has a substrate, and an adhesive material disposed onto the substrate. A pellicle frame is connected to the substrate by way of the adhesive material. The pellicle frame is configured to mount the substrate to an extreme ultraviolet (EUV) reticle.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Mask and method for forming the same
    Patent number: 9651857
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Ta-Cheng Lien, Anthony Yen
  • Semiconductor fin structures and methods for forming the same
    Patent number: 9633905
    Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Integrated high-K/metal gate in CMOS process flow
    Patent number: 9601388
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Metal gate structure of a semiconductor device
    Patent number: 9595443
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Assist feature for a photolithographic process
    Patent number: 9557649
    Abstract: A photolithographic technique includes receiving a mask having a printing feature region, a sub-resolution assist feature (SRAF) region, and a third region. Each region has a different thickness of an absorptive layer disposed therein. The technique also includes exposing the mask to radiation, such that an intensity of radiation reflected by the SRAF region is substantially between an intensity of radiation reflected by the printing feature region and an intensity of radiation reflected by the third region. Using the radiation reflected by the printing feature region, the radiation reflected by the SRAF region, and the radiation reflected by the third region a workpiece is exposed.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chia-Jen Chen, Hsin-Chang Lee, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • System, method and reticle for improved pattern quality in extreme ultraviolet (EUV) lithography and method for forming the reticle
    Patent number: 9558944
    Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Chia-Chen Chen, Jui-Ching Wu, Shang-Chieh Chien, Chia-Jen Chen, Chia-Ching Huang
  • Method and system for inspection of a patterned structure
    Patent number: 9530200
    Abstract: A method and a system for inspection of a patterned structure are provided. In various embodiments, the method for inspection of a patterned structure includes transferring the patterned structure into a microscope. The method further includes acquiring a top-view image of the patterned structure by the microscope. The method further includes transferring the patterned structure out of the microscope and exporting the top-view image to an image analysis processor. The method further includes measuring a difference between a contour of the top-view image and a predetermined layout of the patterned structure by the image analysis processor.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Hsin-Chang Lee
  • METHOD OF MAKING AN EXTREME ULTRAVIOLET PELLICLE
    Publication number: 20160363857
    Abstract: The present disclosure relates to an extreme ultraviolet (EUV) pellicle having a pellicle film connected to a pellicle frame. In some embodiments, the EUV pellicle has a substrate, and an adhesive material disposed onto the substrate. A pellicle frame is connected to the substrate by way of the adhesive material. The pellicle frame is configured to mount the substrate to an extreme ultraviolet (EUV) reticle.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • PROCESS OF MANUFACTURING FIN-FET DEVICE
    Publication number: 20160308027
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chia-Wei CHANG, An-Shen CHANG, Eric Chih-Fang LIU, Ryan Chia-Jen CHEN, Chia-Tai LIN, Chih-Tang PENG
  • Lithography Mask
    Publication number: 20160299419
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 13, 2016
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • Integrated High-K/Metal Gate in CMOS Process Flow
    Publication number: 20160293490
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Application
    Filed: January 29, 2016
    Publication date: October 6, 2016
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Method of making an extreme ultraviolet pellicle
    Patent number: 9442368
    Abstract: The present disclosure relates to a method of forming an extreme ultraviolet (EUV) pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate. A pellicle frame is attached to an upper surface of the substrate, and the substrate is cleaved along the cleaving plane to form a pellicle film attached to the pellicle frame. The method forms the pellicle without using a support structure, which may block EUV radiation and cause substantial non-uniformities in the intensity of EUV radiation incident on an EUV reticle.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Structure and method of photomask with reduction of electron-beam scatterring
    Patent number: 9429835
    Abstract: The present disclosure provides a structure of a photomask. The photomask includes a substrate; and a conductive material layer dispose over the substrate and patterned to include a plurality of openings and a recess structure surrounding the plurality of openings.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Hsin-Chang Lee
  • Extreme Ultraviolet Light (EUV) Photomasks, and Fabrication Methods Thereof
    Publication number: 20160223900
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Tao-Min Huang, Chih-Tsung Shih, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Assist Feature for a Photolithographic Process
    Publication number: 20160195812
    Abstract: A photolithographic technique includes receiving a mask having a printing feature region, a sub-resolution assist feature (SRAF) region, and a third region. Each region has a different thickness of an absorptive layer disposed therein. The technique also includes exposing the mask to radiation, such that an intensity of radiation reflected by the SRAF region is substantially between an intensity of radiation reflected by the printing feature region and an intensity of radiation reflected by the third region. Using the radiation reflected by the printing feature region, the radiation reflected by the SRAF region, and the radiation reflected by the third region a workpiece is exposed.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: TAO-MIN HUANG, CHIA-JEN CHEN, HSIN-CHANG LEE, CHIH-TSUNG SHIH, SHINN-SHENG YU, JENG-HORNG CHEN, ANTHONY YEN
  • FinFET device structure and methods of making same
    Patent number: 9379220
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Cheng-Han Wu, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Composite dummy Gate With conformal Polysilicon layer For FinFet Device
    Publication number: 20160181398
    Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Ryan Chia-Jen Chen, Ming-Ching Chang, Tzu-Yen Hsieh
  • Method of calibrating or exposing a lithography tool
    Patent number: 9373552
    Abstract: A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Chia-Hao Hsu, Kuo-Yu Wu, Chia-Jen Chen, Chao-Cheng Chen
  • Lithography mask
    Patent number: 9366953
    Abstract: The present disclosure provides a lithography mask comprising a substrate, a reflective multiplayer (ML) on the substrate, a barrier layer on the reflective ML, and an absorber layer over the barrier layer. In some embodiments, a thickness of the barrier layer is less than or equal to about 10 nm. In some embodiments, a portion of the absorber layer and a portion of the barrier layer are removed. The present disclosure also provides a method for fabricating a lithography mask, and a method for patterning a substrate using a lithography mask.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen