Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.

Abstract: A wafer cleaning module and a method for cleaning a wafer with the wafer cleaning module are disclosed. For example, the wafer cleaning module includes a wafer chuck to hold a wafer, an ozone source to provide ozone gas towards the wafer, and an ultraviolet (UV) lamp module to provide UV light. The UV lamp module includes a UV light source and a rotatable reflector around the UV light source. The rotatable reflector is movable to adjust an amount of UV light directed towards a surface of the wafer.

Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask outside of a pattern region of the photomask, and the at least one fiducial mark includes identifying information for the photomask. The method includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern. The method includes transferring the pattern from the photomask to a wafer.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Abstract: An photolithographic apparatus includes a particle removing cassette selectively extendable from the processing apparatus. The particle removing cassette includes a wind blade slit and an exhausting slit. The wind blade slit is configured to direct pressurized cleaning material to a surface of the mask to remove the debris particles from the surface of the mask. The exhausting slit collects the debris particles separated from the surface of the mask and contaminants through the exhaust line. In some embodiments, the wind blade slit includes an array of wind blade nozzles spaced apart within the wind blade slit. In some embodiments, the exhausting slit includes array of exhaust lines spaced apart within the exhausting slit.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming sacrificial gate stacks over the substrate; forming a sacrificial fill layer over the sacrificial gate stacks; removing the sacrificial fill layer; forming sidewall spacers besides the sacrificial gate stacks; removing the sacrificial gate stacks; and forming metal gate stacks; wherein the sacrificial fill layers is made of fill materials with a high etch rate selectivity to materials of the sidewall spacers.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures, a gate structure across the fin structures, and a dielectric layer. The gate structure includes a work function layer over the gate dielectric layer, and a contact layer over the work function layer. A portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A top surface of the work function layer and a top surface of the dielectric layer are substantially on a same level. A method for forming a semiconductor structure is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures and a gate structure across the fin structures. The gate structure includes a gate dielectric layer over fin structures, a work function layer over the gate dielectric layer, and a contact layer over the work function layer. In some embodiments, a portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A method for forming a semiconductor structure is also provided.

Abstract: An photolithographic apparatus includes a particle removing cassette selectively extendable from the processing apparatus. The particle removing cassette includes a wind blade slit and an exhausting slit. The wind blade slit is configured to direct pressurized cleaning material to a surface of the mask to remove the debris particles from the surface of the mask. The exhausting slit collects the debris particles separated from the surface of the mask and contaminants through the exhaust line. In some embodiments, the wind blade slit includes an array of wind blade nozzles spaced apart within the wind blade slit. In some embodiments, the exhausting slit includes array of exhaust lines spaced apart within the exhausting slit.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.