Patents by Inventor Chia-Ling Chan
Chia-Ling Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230976Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng CHEN, Chia-Ling CHAN, Liang-Yin CHEN, Huicheng CHANG
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Patent number: 11677028Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.Type: GrantFiled: July 8, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11610885Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.Type: GrantFiled: July 9, 2020Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chia-Ling Chan, Liang-Yin Chen, Huicheng Chang
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Publication number: 20230058699Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
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Publication number: 20220376089Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.Type: ApplicationFiled: July 28, 2022Publication date: November 24, 2022Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
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Patent number: 11495674Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.Type: GrantFiled: December 23, 2019Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
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Patent number: 11456373Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.Type: GrantFiled: April 29, 2020Date of Patent: September 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
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Publication number: 20220285552Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
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Patent number: 11342454Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: GrantFiled: June 22, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
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Patent number: 11264505Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.Type: GrantFiled: September 21, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Yen-Chun Lin
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Patent number: 11018259Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.Type: GrantFiled: May 20, 2016Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yang Lo, Tung-Wen Cheng, Chia-Ling Chan, Mu-Tsang Lin
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Publication number: 20210013337Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.Type: ApplicationFiled: September 21, 2020Publication date: January 14, 2021Inventors: Chia-Ling Chan, Yen-Chun Lin
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Patent number: 10879399Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.Type: GrantFiled: September 19, 2018Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Wei-Yang Lo, Tung-Wen Cheng, Chia-Ling Chan, Mu-Tsang Lin
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Patent number: 10861935Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: GrantFiled: August 5, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
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Publication number: 20200343383Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.Type: ApplicationFiled: July 8, 2020Publication date: October 29, 2020Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20200343242Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.Type: ApplicationFiled: July 9, 2020Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng CHEN, Chia-Ling CHAN, Liang-Yin CHEN, Huicheng CHANG
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Publication number: 20200321465Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
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Patent number: 10784377Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.Type: GrantFiled: September 5, 2018Date of Patent: September 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Yen-Chun Lin
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Publication number: 20200259001Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
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Patent number: 10727226Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.Type: GrantFiled: July 18, 2017Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chia-Ling Chan, Liang-Yin Chen, Huicheng Chang