Patents by Inventor Chia-Ling Chan

Chia-Ling Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PMOS FinFET
    Publication number: 20180175200
    Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 21, 2018
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • INNOVATIVE APPROACH TO MINIMIZE PLASMA DOPING INDUCED FIN HEIGHT LOSS
    Publication number: 20180166341
    Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: Chia-Ling CHAN, Tsan-Chun Wang, Liang-Yin Chen, Huicheng Chang
  • FINFET Device and Methods of Forming
    Publication number: 20180151701
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.
    Type: Application
    Filed: March 29, 2017
    Publication date: May 31, 2018
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170179290
    Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.
    Type: Application
    Filed: May 20, 2016
    Publication date: June 22, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang LO, Tung-Wen CHENG, Chia-Ling CHAN, Mu-Tsang LIN
  • FINFET AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160149040
    Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.
    Type: Application
    Filed: August 6, 2015
    Publication date: May 26, 2016
    Inventors: Wei-Yang LEE, Ting-Yeh CHEN, Chia-Ling CHAN, Chien-Tai CHAN
  • FinFET and method of manufacturing the same
    Patent number: 9343575
    Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Ting-Yeh Chen, Chia-Ling Chan, Chien-Tai Chan
  • FinFET and method of manufacturing the same
    Patent number: 9129988
    Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: September 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Ting-Yeh Chen, Chia-Ling Chan, Chien-Tai Chan