Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Abstract: A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.

Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

Abstract: A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.

Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.

Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.