Patents by Inventor Chia-Ming Hsu

Chia-Ming Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 10925410
    Abstract: A mattress for patient care. The mattress includes a number of compressible cells and a number of sensors corresponding to the number of compressible cells. Each compressible cell is configured to contact, when inflated, a user in a contact area of a plurality of contact areas of the user. Each sensor is configured to generate a number of measurements, wherein each measurement relates to the contact area of a corresponding compressible cell. Each sensor is further configured to send the number of measurements to a pressure control device.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 23, 2021
    Assignee: MedicusTek, Inc.
    Inventors: Chia-Ming Hsu, Yi-Yuan Chen, Tsai-Yu Lin, Lavina Che-Hsuan Thong, Aaron R. Clousing, Yu-Chun Hsu, Lee Lin
  • Publication number: 20210051345
    Abstract: A video coder that implements illumination compensation is provided. The video coder receives a first block of pixels in a first video picture to be coded as a current block, wherein the current block is associated with a motion vector that references a second block of pixels in a second video picture as a reference block. The video coder performs inter-prediction for the current block by using the motion vector to generate a set of motion-compensated pixels for the current block. The video coder modifies the set of motion-compensated pixels of the current block by applying a linear model that is computed based on neighboring samples of the reference block and of the current block. The neighboring samples are identified based on a position of the current block within a larger block.
    Type: Application
    Filed: April 29, 2019
    Publication date: February 18, 2021
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG
  • Patent number: 10910277
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20210028069
    Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • Publication number: 20210018381
    Abstract: A pressure sensing device includes a substrate, at least a pressure sensing module, and a packaging layer. The pressure sensing module is arranged at the substrate including a plurality of conductive units, a plurality of pressure sensing blocks and a plurality of buffer units. Each conductive unit has a first electrode and a second electrode. The pressure sensing blocks are respectively arranged at the conductive units. Each pressure sensing block has a circuit structure that electrically connects the first electrode and the second electrode of each corresponding conductive unit. Each buffer unit is arranged between each corresponding conductive unit and each corresponding pressure sensing block comprising a plurality of buffer bumps arranged in an array at the first electrode and the second electrode of each corresponding conductive units. The packaging layer is bonded to the substrate, the conductive units and the pressure sensing blocks.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 21, 2021
    Applicant: MEDX TECHNOLOGY INC.
    Inventors: Chia-Ming Hsu, Chun Lin
  • Publication number: 20200403082
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
  • Publication number: 20200396444
    Abstract: A method and apparatus for video coding using Intra prediction are disclosed. In one method, a first prediction sample in an immediately right column of the current block and a second prediction sample in an immediately below row of the current block are derived using angular prediction. The first prediction sample and a left column reference sample in the same row as the first prediction sample are interpolated to generate a horizontal predictor. The second prediction sample and an above-row reference sample in the same column as the second prediction sample are interpolated to generate a vertical predictor. The vertical predictor and the horizontal predictor are linearly combined to generate an angular-planar prediction sample. In another method, a first predictor is generated using angular prediction and a second predictor is generated using planar prediction. The first predictor and the second predictor are linearly combined to generate a fused Intra predictor.
    Type: Application
    Filed: October 26, 2018
    Publication date: December 17, 2020
    Inventors: Chia-Ming TSAI, Han HUANG, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 10867963
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20200345169
    Abstract: The disclosure relates to an extraction device for extracting soluble favors from raw materials that are distributed within liquid. The extraction device includes a first container, a second container, a valve, and an air suction device. The second container is configured for storing the mixture of the raw materials and the liquid. The valve is connected to the second container and the first container. The air suction device is connected to the first container and configured to decrease the internal pressure of the first container to a predetermined value. When the internal pressure of the first container reaches the predetermined value, the valve is activated to connect the first container to the second container. The disclosure also relates to an extracting method for using the extraction device.
    Type: Application
    Filed: December 11, 2019
    Publication date: November 5, 2020
    Inventors: PEI-LING LAI, CHAO HSUAN CHIU, YING LUN HSU, YU-FANG CHEN, CHIA MING LIANG, YU-KAI SU
  • Publication number: 20200348355
    Abstract: A reliability determination method, which is configured to test a batch of semiconductor devices, includes: obtaining a Welbull distribution of lifetime of the batch of semiconductor devices; dividing the Welbull distribution into at least a first section and a second section, wherein the first section and the second section meet a confidence interval; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, in which the first trend line has a first slope and the second trend line has a second slope; determining the first slope exceeds a second slope; and determining a predicted reliability of the batch of the semiconductor device under a target quality level according to the first section.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Sheng-Hui LIANG, Huang-Lang PAI, Chia-Ming HSU, Chia-Lin CHEN
  • Publication number: 20200350416
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Patent number: 10804163
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20200321238
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
  • Patent number: 10797157
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
  • Publication number: 20200294965
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20200266297
    Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen
  • Patent number: 10717796
    Abstract: Extruded films comprising ethylene vinyl alcohol copolymer (EVOH) with substantially no blow holes therein, are formed by using a pellet feed to the extruder wherein 90-100 wt. % of the pellets pass through an ASTM size 5 sieve and 0-10 wt. % of the pellets are finer than a number 10 mesh (ASTM Sieve size). Uniform feeding to and through the extruder with a lack of bridging of the EVOH pellet feed have been observed.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 21, 2020
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Huan Ming Chang, Weng Shing Lin, Chih Chieh Liang, Chia Hao Hsu
  • Publication number: 20200228832
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. According to one method, a current block is partitioned into a plurality of sub-blocks using SDIP (Short Distance Intra Prediction mod). A first Bs (boundary strength) for an internal block boundary of the plurality of sub-blocks is determined by setting the first Bs to a second Bs of an Intra-coded boundary block of the current block. De-blocking process is applied, using the first Bs, to reconstructed samples across the internal block boundary of the plurality of sub-blocks to generate filtered-reconstructed samples. In another method, the current block is partitioned into two sub-blocks using SBT (sub-block transform) horizontally or vertically and the first Bs (boundary strength) is determined for an internal block boundary between the two sub-blocks by setting the first Bs to a second Bs of a non-zero cbf (coded block flag) block of the two sub-blocks in step.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 16, 2020
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN