Patents by Inventor Chia-Ming Hsu

Chia-Ming Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121705
    Abstract: A wireless communication method includes: categorizing a plurality of different beacon elements into a first group of elements and a second group of elements; generating a beacon frame, which is configured to carry the first group of elements, wherein the beacon frame is compliant to at least one legacy generation of Wi-Fi technology; generating a second frame, which is configured to carry the second group of elements, wherein the second frame is compliant to a non-legacy generation of Wi-Fi technology rather than the at least one legacy generation of Wi-Fi technology; and sending the beacon frame and the second frame.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chien-Fang Hsu, Chia-Ming Chang
  • Patent number: 11942467
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Patent number: 11930174
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11916151
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
  • Patent number: 11908749
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20240027281
    Abstract: A drive system thermal temperature rise test and compensation system. The system has an optical non-contact type sensing head mounted on a main shaft of a machine tool, and a sensing center is formed in the center of the sensing head. A platform driven by a transmission device of the machine tool is provided with plural ball lens devices, and a temperature sensor for transmitting temperature data externally is further provided on the transmission device. After the machine tool sequentially records an original point coordinate for each ball lens center by using the sensing head, the sensing head is cyclically and sequentially moved to the original point coordinate of each ball lens, so as to measure a displacement error between the sensing center and the ball lens center resulted from thermal shifts of the transmission device, as well as capable of measuring multiaxial errors and using various axial temperatures for compensation.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 25, 2024
    Inventors: Wen-Yuh JYWE, Tung-Hsien HSIEH, Chia-Ming HSU, Yu-Wei CHANG, Sen-Yi HUANG, Ching-Ying CHIU, Pin-Wei LU, Jheng-Jhong ZENG
  • Patent number: 11861282
    Abstract: A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu
  • Publication number: 20230347553
    Abstract: A method for making foamed shoe materials includes mixing r-PET and EVA with a compatibilizer for melt modification, a new polymer alloy is formed. The polymer alloy is then extruded into strips with an screw extruder under a temperature of 160° C. to 245° C. and an average shear rate of 100/sec to 300/sec, and at an extrusion rate of 100 kg/hr to 250 kg/hr. Simultaneously, the temperature of the screw in the extrusion process is controlled to rise from 160° C. to 245° C., then decrease to less than 240° C., so as to produce composite material masterbatches with good compatibility between recycled PET and EVA, which are used to produce foamed shoe materials, thus achieving the purpose of reusing recycled PET, reducing carbon emissions, and protecting the environment. Furthermore, it reduces the demand for fresh PET materials, thereby reducing the demand for petrochemical raw materials.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Inventors: Chih-Jen Hsu, Chia-Ming Hsu, Yi-Ju Huang
  • Patent number: 11738529
    Abstract: An environmentally friendly shoe component of a shoe includes scraps and an elastic material layer within which the scraps are distributed, the scraps include bottle scraps made by crushing plastic bottles, the elastic material layer is made of thermosetting polyurethane elastomer, and at least a part of the scraps is visible by a human's naked eye.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: August 29, 2023
    Assignee: CCILU International Inc.
    Inventors: Chih-Jen Hsu, Chia-Ming Hsu, Chen-En Kao
  • Publication number: 20230170397
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Publication number: 20230113014
    Abstract: A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20230079483
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • Publication number: 20230043635
    Abstract: A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.
    Type: Application
    Filed: March 14, 2022
    Publication date: February 9, 2023
    Inventors: Pei-Yu Chou, Chia-Ming Hsu, Tze-Liang Lee
  • Publication number: 20230039490
    Abstract: A lung breathing chip and cell stretching culture platform and an operating method thereof are disclosed. The lung breathing chip and cell stretching culture platform controls the output of the motor by programming, stretches the micro-fluidic chip by the cam component, changes the size of the cam component and the frequency of the motor rotation to change the stretching frequency and the amount of stretching to simulate the breathing of the lungs in different states, uses liquid electrophoresis technology to arrange the cells in the biocompatible hydrogel and the hydrogel three-dimensionally to imitate the three-dimensional cell tissue, and injects drugs through the dynamic perfusion system to realize the drug testing platform that the cells of the chip bionic lung tissue are stretched.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Applicants: NATIONAL TSING HUA UNIVERSITY, TAIPEI MEDICAL UNIVERSITY
    Inventors: Cheng-Yu HUANG, Chun-Hui SUNG, Pin-Tzu LAI, Chia-Ming HSU, Yi-Ying LIANG, Kang-Yun LEE, Shu-Chuan HO, Weilun SUN, Cheng-Hsien LIU
  • Patent number: 11569362
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu, Jyh-Huei Chen
  • Patent number: 11568122
    Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu
  • Publication number: 20230008020
    Abstract: A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming HSU, Da-Wen LIN, Clement Hsingjen WANN