Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A heat dissipation assembly is provided. The heat dissipation assembly includes a heat source, an upper cover, and a heat dissipation device. The upper cover includes a first upper cover surface and a second upper cover surface. The first upper cover surface receives the thermal energy from the heat source. The heat dissipation device is located under the upper cover and adjacent to the second upper cover surface to cool the second upper cover surface. The upper cover is a thermoelectric generator chip.

Abstract: A method for multi-spectral scattering-matrix tomography includes a step of splitting an input light signal into an incident light signal and a reference light signal. The sample light signal is directed to a sample in either a reflection configuration or a transmission configuration such that an output light signal includes light scattered from or transmitted through the sample. The incident signal and the reference light signal are directed to a camera angled to allow for amplitude and phase to be calculated by off-axis holography. A total light signal is measured with a camera that is a coherent sum of the reference light signal and the output signal. The total light signal for each light frequency and each incident angle are collected as collected total light signal data. A computing device derives an image of the sample from a calculated reflection matrix or transmission matrix or both of them.

Abstract: A circuit includes an operational amplifier configured to output a driving signal according to a feedback voltage associated with an output voltage and a reference voltage, a pass gate circuit comprising switches in current paths, and hysteresis comparators connected to the operational amplifier and configured to generate control signals to separately turn on or off the switches in the current paths in response to the driving signal.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.

Abstract: An amplification circuit may include an input terminal, an output terminal, a first amplification path and a second amplification path. The first amplification path may include a first transistor and a second transistor cascoded between the input terminal and the output terminal. The second amplification path may include a third transistor coupled between the input terminal and the output terminal. A control terminal of the first transistor and a control terminal of the third transistor are coupled to the input terminal. A first terminal of the second transistor may be coupled to a second terminal of the first transistor. The first amplification path and the second amplification path may be configured to operate independently of each other. A second terminal of the third transistor and a second terminal of the second transistor are coupled to a common node. In the second amplification path, the transistor closest to the common node is a common-source transistor or a common-emitter transistor.

Abstract: The application discloses a compilation method, a data processing method and an apparatus thereof. Data representing a first graph characterizing the operations of a first neural network is obtained. The data representing the first graph is processed to transform the first graph into a second graph. A set of instructions for characterizing the second graph is generated. The set of instructions is provided to one or more hardware platforms.

Abstract: A protein analysis platform includes a platform body comprising: a gel working unit provided in a top portion of the platform body and comprising a gel accommodation area for accommodating at least one gel; at least one electrophoresis tank provided along a side of the gel accommodation area and provided with at least one electrode; and a blotting layer stack provided in a bottom portion of the gel working unit and comprising an electrode layer; wherein a removable bottom plate is provided between the gel working unit and the blotting layer stack and detachably corresponds to a bottom side of the gel accommodation area. The protein analysis platform is used for western blotting or next-generation western blotting, wherein the protein analysis platform can quickly complete steps such as gel casting, electrophoresis, and blotting in one platform.

Abstract: A detection device includes a substrate, a light source, a detection module, and a heat dissipation module. The substrate includes a first base plate, a second base plate, and at least one connecting portion connecting the first base plate to the second base plate. The light source is disposed on the first base plate. The detection module is disposed on the second base plate. The first base plate has a first surface towards the at least one connecting portion, and the at least one connecting portion has a second surface towards the first base plate. The second surface is connected to a portion of the first surface. The heat dissipation module is disposed on the at least one connecting portion and/or the second base plate, and the influence of heat on proper operation of the detection device is thus prevented.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A radio-frequency front-end module includes a common node, a first node, a second node, a third node, a first path, a second path and a third path. The first path may be disposed between the common node and the first node and may include an inductor. The second path may be disposed between the common node and the second node and may include a second switch. The third path may be disposed between the common node and the third node and include a third switch. When the second switch is turned on, the second path may transceive the second signal and the third switch may be turned off, such that the inductor in the first path may provide an inductive impedance for the second signal, and the third switch may provide a capacitive impedance for the second signal.

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: An auto-regressive method for a large language model includes receiving a hidden state associated with at least one token, generating key data, first value data, and query data according to a received hidden state, generating first positionally encoded key data by encoding the key data positionally, generating positionally encoded query data by encoding the query data positionally, performing first element-wise dot product operations according to the first positionally encoded key data, the positionally encoded query data, and second positionally encoded key data to generate an attention score, performing second element-wise dot product operations according to the first value data, the attention score, and second value data to generate an attention output, and adding the attention output and the hidden state to generate an updated hidden output.

Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: An integrated circuit (IC) device includes a substrate having a front side, a back side below the front side, and first functional circuitry and a first electrostatic discharge (ESD) clamp circuit on the front side of the substrate. The IC device further includes a first connection tower that extends below the back side of the substrate and is connected to an input/output pad below the back side of the substrate, and one or more first front side conductors and one or more first front side vias which connect the first buried connection tower to the first functional circuitry and to the first ESD clamp circuit.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Abstract: A processor, an operation method, and a load-store device are provided. The processor is adapted to access a memory. The processor includes a vector register file (VRF) and the load-store device. The load-store device is coupled to the VRF. The load-store device performs a strided operation on the memory. In a current iteration of the strided operation, the load-store device reads a plurality of first data elements at a plurality of discrete addresses in the memory and writes the first data elements into the VRF, or the load-store device reads a plurality of second data elements from the VRF and writes the second data elements into a plurality of discrete addresses in the memory during the current iteration of the strided operation.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first n-type transistor having a first threshold voltage and including a first gate dielectric layer, and a second n-type transistor having a second threshold voltage and including a second gate dielectric layer. The first threshold voltage is lower than the second threshold. Each of the first gate dielectric layer and the second gate dielectric layer contains fluorine and hafnium. The first gate dielectric layer has a first average fluorine concentration and a first average hafnium concentration. The second gate dielectric layer has a second average fluorine concentration and a second average hafnium concentration. A first ratio of the first average fluorine concentration to the first average hafnium concentration is greater than and a second ratio of the second average fluorine concentration to the second average hafnium concentration.