Patents by Inventor Chia-Wei Hsu

Chia-Wei Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071767
    Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.
    Type: Application
    Filed: January 6, 2023
    Publication date: February 29, 2024
    Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
  • Patent number: 11915979
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11881409
    Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Lung-En Kuo, Chia-Wei Hsu
  • Publication number: 20240004647
    Abstract: A vector processor with a vector reduction method and an element reduction method is provided. The vector processor includes a vector register file and first and second lanes. In the vector reduction method, the first lane loads a first operand and a first part of a second operand based on a first state parameter and performs a first reduction operation on the first operand and the first part of the second operand to generate a first part of a first reduction result. The second lane loads a second part of the second operand based on the first state parameter and uses the second part of the second operand as a second part of the first reduction result. One of the first lane or the second lane performs a second reduction operation on the first and second parts of the first reduction result to generate a second reduction result.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventor: Chia-Wei Hsu
  • Patent number: 11862468
    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
  • Publication number: 20230418614
    Abstract: A processor, an operation method, and a load-store device are provided. The processor is adapted to access a memory. The processor includes a vector register file (VRF) and the load-store device. The load-store device is coupled to the VRF. The load-store device performs a strided operation on the memory. In a current iteration of the strided operation, the load-store device reads a plurality of first data elements at a plurality of discrete addresses in the memory and writes the first data elements into the VRF, or the load-store device reads a plurality of second data elements from the VRF and writes the second data elements into a plurality of discrete addresses in the memory during the current iteration of the strided operation.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventor: Chia-Wei Hsu
  • Publication number: 20230377891
    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
  • Publication number: 20230352338
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Publication number: 20230317523
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Ying LAI, Chia-Wei HSU, Tsung-Da LIN, Chi On CHUI
  • Publication number: 20230299576
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Publication number: 20230299088
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.
    Type: Application
    Filed: April 14, 2023
    Publication date: September 21, 2023
    Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
  • Patent number: 11756832
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11750239
    Abstract: A front end module includes a first radio frequency (RF) terminal, a second RF terminal, a third RF terminal, a transmission path and a reception path. The transmission path is formed between the first RF terminal and the third RF terminal. The reception path is formed between the first RF terminal and the second RF terminal. The reception path includes a first set of switches, a second set of switches, a third set of switches and an amplifier. An amplifier is coupled to the second set of switches and the second RF terminal. The third set of switches is coupled to the first set of switches and the second RF terminal. When a transmission signal is transmitted to the first RF terminal via the transmission path, the first set of switches, the second set of switches and the third set of switches are turned off.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: September 5, 2023
    Assignee: RichWave Technology Corp.
    Inventors: Chia-Wei Hsu, Chih-Sheng Chen, Yu-Hsuan Chao
  • Patent number: 11742236
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Patent number: 11710962
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
    Type: Grant
    Filed: May 29, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 11664381
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yao Huang, Wun-Jie Lin, Chia-Wei Hsu, Yu-Ti Su
  • Publication number: 20230136392
    Abstract: A front end module includes a first radio frequency (RF) terminal, a second RF terminal, a third RF terminal, a transmission path and a reception path. The transmission path is formed between the first RF terminal and the third RF terminal. The reception path is formed between the first RF terminal and the second RF terminal. The reception path includes a first set of switches, a second set of switches, a third set of switches and an amplifier. An amplifier is coupled to the second set of switches and the second RF terminal. The third set of switches is coupled to the first set of switches and the second RF terminal. When a transmission signal is transmitted to the first RF terminal via the transmission path, the first set of switches, the second set of switches and the third set of switches are turned off.
    Type: Application
    Filed: December 20, 2021
    Publication date: May 4, 2023
    Applicant: RichWave Technology Corp.
    Inventors: Chia-Wei Hsu, Chih-Sheng Chen, Yu-Hsuan Chao
  • Publication number: 20230128254
    Abstract: A method for multi-spectral scattering-matrix tomography includes a step of splitting an input light signal into an incident light signal and a reference light signal. The sample light signal is directed to a sample in either a reflection configuration or a transmission configuration such that an output light signal includes light scattered from or transmitted through the sample. The incident signal and the reference light signal are directed to a camera angled to allow for amplitude and phase to be calculated by off-axis holography. A total light signal is measured with a camera that is a coherent sum of the reference light signal and the output signal. The total light signal for each light frequency and each incident angle are collected as collected total light signal data. A computing device derives an image of the sample from a calculated reflection matrix or transmission matrix or both of them.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 27, 2023
    Inventors: Chia Wei HSU, Zeyu WANG, Yiwen ZHANG
  • Publication number: 20230115634
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.
    Type: Application
    Filed: May 3, 2022
    Publication date: April 13, 2023
    Inventors: Tsung-Da Lin, Chia-Wei Hsu, Chi On Chui
  • Publication number: 20230081415
    Abstract: A lens system having reduced physical size. The lens system includes multiple metalenses, lenses with metasurfaces, that integrate the lens and the free space and compress them into multiple layers of metasurfaces, significantly reducing the overall volume and weight of the imaging system while increasing its efficiency. The lens system also provides for tools that can accurately model 3D multilayer metasurfaces, carry out inverse design to find the optimal and fault-tolerant structure, fabricate the metasurfaces with multi-project wafer service, assemble them with a 3D-printed holder, and characterize the performance of the resulting ultra-compact imaging system.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 16, 2023
    Inventors: Chia Wei Hsu, Shiyu Li, Mahsa Torfeh