Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Abstract: Certain embodiments are directed to compositions and methods for solving problems associated with measuring T:G mispairs, U:G mispairs and other 5-substituted uracil mispairs. Certain embodiments are directed to a hybrid enzyme that is capable of finding and cutting the T of the T:G mispair or other mispaired uracil analogs creating a method for their measurement. In certain embodiments the hybrid enzyme is a fusion of a human thymine DNA glycosylase (TDG) activator segment and a catalytic domain of an archaeal thermophilic thymine glycosylase (tTDG).

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A detection device includes a cover, a detection module, and a light source. The cover includes a top wall and a sidewall connected to the top wall. The top wall and the sidewall cooperatively define a receiving cavity. The sidewall includes a first portion close to the top wall and a second portion away from the top wall. The detection module is disposed on the top wall. The light source is disposed on the second portion. The influence of heat on proper operation of the detection device is prevented.

Abstract: A detection device includes a substrate, a light source, a detection module, and a heat dissipation module. The substrate includes a first base plate, a second base plate, and at least one connecting portion connecting the first base plate to the second base plate. The light source is disposed on the first base plate. The detection module is disposed on the second base plate. The first base plate has a first surface towards the at least one connecting portion, and the at least one connecting portion has a second surface towards the first base plate. The second surface is connected to a portion of the first surface. The heat dissipation module is disposed on the at least one connecting portion and/or the second base plate, and the influence of heat on proper operation of the detection device is thus prevented.

Abstract: The present disclosure provides electronic device and control method thereof. The electronic device includes input circuit and processor. The input circuit includes key switches arranged in array. The processor is coupled to the key switches through column lines and row lines and is configured to: detect part of the row lines and part of the column lines coupled to at least one turned-on key switch; assign one of the part of the row lines and the part of the column lines as scan line group, and assign the other of the part of the row lines and the part of the column lines as return line group; input corresponding scan signal to corresponding scan line of the scan line group; and detect whether the return line group outputs the corresponding scan signal, to confirm position of the at least one turned-on key switch.

Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

Abstract: The mask data corresponding to each data element of the issued instruction may be handled by a mask queue, where only the valid mask data are stored to the mask queue. The mask data of multiple vector instructions may be stored in the mask queue. The corresponding mask data may be accessed from the mask queue when the vector instruction(s) is dispatched from the execution queue to the functional unit for execution. In the case of 512-bit wide mask data is needed, the issuing of the vector instruction from the decode/issue unit to the execution queue may be stalled until the mask queue is available. In some embodiments, one mask queue may be dedicated to one execution queue. Alternatively, one mask queue may be shared between two different execution queues. In the disclosure, resources are conserved without dedicating additional storage space for handling mask data of the vector instruction.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

Abstract: A method is disclosed including analyzing a layout netlist including a first set of nodes against a schematic netlist including a second set of nodes. Each node of the first and second sets of nodes is assigned a matching type for identifying matching nodes between the first and second sets of nodes. The method includes determining one or more unmatched nodes between the first set of nodes and the second set of nodes based on the matching type. The method includes generating a convergence graph comprising nodes of the first set of nodes that have a corresponding matching node in the second set of nodes based on the matching type, and the one or more unmatched nodes.

Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

Abstract: An annular reinforcing structure for the reinforcement of a supporting structure of a construction is provided. The annular reinforcing structure includes an outer frame body, an inner frame body and an elastic body. The inner frame body is connected to the outer frame body and positioned therein. The inner frame body and the outer frame body together define an annular space. The elastic body is accommodated in the annual space between the inner frame body and the outer frame body.

Abstract: An annular reinforcing structure for the reinforcement of a supporting structure of a construction is provided. The annular reinforcing structure includes an outer frame body, an inner frame body and an elastic body. The inner frame body is connected to the outer frame body and positioned therein. The inner frame body and the outer frame body together define an annular space. The elastic body is accommodated in the annual space between the inner frame body and the outer frame body.