Patents by Inventor Chia-Wei Tu

Chia-Wei Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867975
    Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Yi-Sheng Wang
  • Publication number: 20200286919
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Inventors: HSUEH-CHIH CHOU, CHIA HAO TU, SANG HOO DHONG, LEE-CHUNG LU, LI-CHUN TIEN, TING-WEI CHIANG, HUI-ZHONG ZHUANG
  • Patent number: 10770366
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Publication number: 20200279802
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 10685982
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien, Ting-Wei Chiang, Hui-Zhong Zhuang
  • Patent number: 10658290
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 10622510
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Patent number: 10622509
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Publication number: 20200088786
    Abstract: A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Shiang-Ruei SU, Liang-Chen LIN, Chia-Wei TU
  • Publication number: 20200091027
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Patent number: 10510635
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Patent number: 10495687
    Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu
  • Patent number: 10453818
    Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Chia-Wei Tu, Yian-Liang Kuo, Ru-Ying Huang
  • Publication number: 20190287190
    Abstract: A method of battery charging is to be implemented by an energy station communicable with a cloud server that stores reference battery identifiers. The method includes: detecting a provided battery identifier of a battery, and transmitting the provided battery identifier to the cloud server so as to enable the cloud server to determine one of the reference battery identifiers that matches the provided battery identifier, and to determine to which one of first and second lease codes the one of the reference battery identifiers thus determined corresponds; and being controlled to charge the battery when it is determined that the one of the reference battery identifiers thus determined by the cloud server corresponds to the first lease code.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Chia-Cheng TU, Chi-Wei TIEN, Chien-Hung CHEN
  • Publication number: 20190273071
    Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Yi-Sheng Wang
  • Publication number: 20190259700
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 22, 2019
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 10340258
    Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Yi-Sheng Wang
  • Publication number: 20190189836
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Publication number: 20190189837
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Patent number: RE47977
    Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 5, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Tse-Hung Wu, Chao-Kai Tu, Chia-Wei Su