Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.

Abstract: A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.

Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: A method includes forming a polymer layer over a passivation layer, wherein the passivation layer further comprises a portion over a metal pad. The polymer layer is patterned to form an opening in the polymer layer, wherein exposed surfaces of the polymer layer have a first roughness. A surface treatment is performed to increase a roughness of the polymer layer to a second roughness greater than the first roughness. A metallic feature is formed over the exposed surface of the polymer layer.