Patents by Inventor Chia-Wen Liang
Chia-Wen Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240077479Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Applicant: DeepBrain Tech. IncInventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20230397511Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Harry-Hak-Lay Chuang, Chia Wen Liang, Chang-Chih Huang, Han-Yu Chen, Kuo-Chyuan Tzeng, Tsung-Hao Yeh
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Publication number: 20230067962Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.Type: ApplicationFiled: August 28, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alexander KALNITSKY, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Chia Wen LIANG, Li-Feng TENG
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Patent number: 9312359Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: GrantFiled: August 10, 2015Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Publication number: 20150349088Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Patent number: 9136348Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: GrantFiled: March 12, 2012Date of Patent: September 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Patent number: 8999830Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: December 19, 2013Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8952451Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: GrantFiled: December 20, 2013Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140127892Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: ApplicationFiled: December 19, 2013Publication date: May 8, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8704294Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: June 13, 2011Date of Patent: April 22, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140103443Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20130277754Abstract: The present invention provides a resistor structure including a substrate, an ILD layer, a transistor and a resistor. The substrate includes a resistor region and an active region. The ILD layer is disposed directly on the substrate. The transistor is disposed in the active region in the ILD layer wherein the transistor includes a metal gate. The resistor is disposed in the resistor region above the ILD layer, wherein the resistor directly contacts the ILD layer.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Inventors: Chia-Wen Liang, Yi-Chung Sheng, Shih-Chieh Hsu, Yao-Chang Wang, Chi-Horn Pai, Jie-Ning Yang, Chi-Sheng Tseng
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Publication number: 20130234261Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: ApplicationFiled: March 12, 2012Publication date: September 12, 2013Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Publication number: 20120313178Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20110156156Abstract: A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang
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Patent number: 7682890Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.Type: GrantFiled: August 18, 2006Date of Patent: March 23, 2010Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Shyh-Fann Ting, Tzyy-Ming Cheng, Chia-Wen Liang
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Patent number: 7622344Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.Type: GrantFiled: July 17, 2007Date of Patent: November 24, 2009Assignee: United Microelectronics Corp.Inventors: Chia-Wen Liang, Cheng-Tung Huang, Shyh-Fann Ting, Chih-Chiang Wu, Shih-Chieh Hsu, Li-Shian Jeng, Kun-Hsien Lee, Meng-Yi Wu, Wen-Han Hung, Tzyy-Ming Cheng
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Patent number: 7585790Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.Type: GrantFiled: July 20, 2006Date of Patent: September 8, 2009Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang, Neng-Kuo Chen