Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Abstract: A method of fabricating a self-aligned capacitor of a DRAM cell is provided. First, a landing pad and a bit line are formed on a semiconductor substrate. An insulating layer is formed on the landing pad and the bit line. A photoresist layer is formed on the insulating layer and the pattern of the photoresist layer is transferred to the insulating layer. A via hole is formed in the insulating layer using the photoresist layer as a mask to expose the landing pad. Spacers are formed on the sidewalls of the via hole by deposition and self-align etching back. A conductive layer is formed in the via hole. The conductive layer on the insulating layer is removed to form a bottom electrode of a capacitor.

Abstract: A method for simultaneously forming a bit-line contact and a node contact first forms a polysilicon layer and a first insulator on a substrate, and then patterns patterning the polysilicon layer and the first insulator, wherein the substrate consists of an active area and an isolation area. Next, a second insulator is formed on the exposed substrate and the first insulator. Then, by forming a photoresist layer on the second insulator and patterning the photoresist layer, a pattern containing a bit-line contact pattern and a node contact pattern is transferred onto the second insulator. By performing an etching back process on the second insulator, the bit-line contact and the node contact are formed simultaneously in a self-aligned way.

Abstract: A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.

Abstract: The present invention provides a fabricating method and structure of a dynamic random access memory. In this method, a substrate having a transistor thereon is provided. A bit line is formed on the substrate. The bit line is electrically coupled with the transistor through a contact hole. A second dielectric layer having a node contact opening is formed on the bit line. An etching step is performed to etch the bit line. A concave surface is formed on the sidewall of the bit line. Spacer layers are formed on the sidewalls of the node contact opening. Each spacer layer is used to insulate the concave surface. Thus, from the top-view layout, a portion of the node contact opening can overlap with the bit line. Thus, the size of DRAM is effectively reduced.

Abstract: A method for forming self-aligned landing pads on a substrate containing a pre-formed first conducting layer and a pre-formed first insulator, wherein the substrate further includes a patterned second insulator to form contact openings exposing the substrate. A second conducting layer in formed on the substrate. A photoresist layer is formed on the second conducting layer and patterned to transfer the pattern onto the second conducting layer. The second conducting layer is patterned to expose the first insulator. Then, an etching back process is performed to selectively remove more of the second conducting layer in order to form the self-aligned landing pads.

Abstract: A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.

Abstract: The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode.

Abstract: A method for minimizing the dimension of a contact forms a thick dielectric layer on a provided substrate first, and then forms a contact on the first dielectric layer and expose the substrate by performing a slope etching process. The contact with the target contact size is obtained by partially removing the thick dielectric layer. Since the target contact size is obtained by a self-aligned method, the upper diameter of the contact is not limited by a conventional fabrication process. Furthermore, after a contact is formed, it is optional to fill the contact with filler. Even after a desired contact is formed in the case that filler is used, the remains of the filler can be either kept or removed depending on the conductivity of the filler.

Abstract: A method for forming a DRAM capacitor that utilizes silicon nitride spacers on two occasions to perform self-aligned contact window etching operations. Furthermore, on the second etching operation, one less photomask is required for the etching of the second via. In addition, a silicon nitride layer over the first polysilicon layer has a smaller thickness than the usual oxide layer in a conventional method of manufacture. Consequently, a shallower contact step height for the capacitor, which is beneficial to the production of miniaturized devices, is obtained. Finally, the tri-fork shaped capacitor structure further increases the surface area of the capacitor so that the capacitance of the DRAM capacitor is increased.

Abstract: A semiconductor fabrication method is provided for fabricating a capacitor electrode structure in an integrated circuit such as a DRAM (dynamic random-access memory) device to serve as a data storage capacitor for the DRAM device. According to this method, a self-aligned process is used to form the bottom electrode of each data storage capacitor of the DRAM device. The first step is to form a first insulating layer over the substrate, which is then selectively removed to form contact windows. Next, a plurality of polysilicon plugs are formed in these contact windows, with the top surfaces thereof being below the top surface of the first insulating layer by a predefined depth. After this, sidewall spacers are formed on the sidewalls of the remaining void portions of the contact windows. After bit lines are formed, another insulating layer is deposited and then selectively removed to form electrode-pattern openings to expose the polysilicon plug that is to be connected to the bottom electrode of the capacitor.

Abstract: A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.

Abstract: A method of forming a self-aligned contact for a transistor formed on a substrate. A self-aligned silicide layer is formed on the surface of a source/drain region of the transistor. A silicon oxide/silicon nitride layer is formed over the transistor. Then, a planarization process is performed to fill a trench between gates with, for example, borophosphosilicate glass. In particular, wet etching using a 20:1 buffered oxide etchant is performed to increase the selectivity of the silicon oxide/silicon nitride layer.