Abstract: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

Abstract: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Abstract: A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

Abstract: A method of fabricating metal-oxide-semiconductor (MOS) transistor devices is disclosed. A semiconductor substrate is provided. A gate dielectric layer is formed. A gate electrode is stacked on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. Using the gate electrode and the silicon nitride spacer as an implantation mask, a source/drain is implanted into the substrate. After the source/drain implant, the silicon nitride spacer is then stripped. A silicide layer is formed on the source/drain region. Subsequently, a silicon nitride cap layer is deposited. The silicon nitride cap layer has a specific stress status.

Abstract: The present invention relates to a method of fabricating strained silicon channel complementary metal oxide semiconductor (CMOS) transistor by using an etching process and a planarization process such as a chemical mechanical polishing (CMP) process, and a structure thereof. The present invention is able to resolve the problem of overlap region between the stressed layers. The present invention is also able to improve the process yield and reduce the fabrication cost.

Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and than several IO devices and several core devices are formed on the substrate, wherein those IO devises include IO PMOS and IO NMOS, and those core devises include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.

Abstract: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

Abstract: A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.

Abstract: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.

Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.

Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal layers through the via plugs. The fuse layer includes at least two separate blocks and at least a connecting block. For the current flowing through the separated blocks in a zig-zag path, of the fuse structure provides at least a fusing point or more than one fusing points. In this way, the negative impact of the single failed fuse can be reduced, thus increasing the reliability of the fuse structure. Also the damage to the devices adjacent to the fuse due to the heat generated by the current can be prevented because when the heat generated during the fuse blowing process will be conducted to the adjacent blocks to facilitate heat dissipation.

Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal layers through the via plugs. The fuse layer includes at least two separate blocks and at least a connecting block. For the current flowing through the separated blocks in a zig-zag path, of the fuse structure provides at least a fusing point or more than one fusing points. In this way, the negative impact of the single failed fuse can be reduced, thus increasing the reliability of the fuse structure. Also the damage to the devices adjacent to the fuse due to the heat generated by the current can be prevented because when the heat generated during the fuse blowing process will be conducted to the adjacent blocks to facilitate heat dissipation.