Abstract: Aspects of the disclosure provide a video decoding system. The video decoding system can include a decoder core configured to selectively decode independently decodable tiles in a picture, each tile including largest coding units (LCUs) each associated with a pair of picture-based (X, Y) coordinates or tile-based (X, Y) coordinates, and memory management circuitry configured to translate one or two coordinates of a current LCU to generate one or two translated coordinates, and to determine a target memory space storing reference data for decoding the current LCU based on the one or two translated coordinates.

Abstract: A multi-core video decoder system has a syntax parser, a storage device, a plurality of video decoder cores and a control unit. The syntax parser performs syntax parsing upon an incoming encoded video bitstream to derive required information of each picture to be decoded. The storage device buffers the required information of each picture. The control unit controls the video decoder cores to load required information of a plurality of coding rows in a picture from the storage device and then decode the coding rows in the picture, respectively.

Abstract: A method and apparatus for video encoding or decoding used by a video encoder or decoder respectively are disclosed. In one method, input data associated with a video sequence are received. A current sequence header for a current picture is determined. Whether the current sequence header corresponds to a first sequence header or a second sequence header is determined. If the current sequence header corresponds to the second sequence header, one or more syntax values of a syntax set associated with the first sequence header are assigned to corresponding one or more syntax values of the syntax set associated with the current sequence header. The current picture is then encoded or decoded according to the current sequence header.

Abstract: A method and apparatus of sharing an on-chip buffer or cache memory for a video coding system using coding modes including Inter prediction mode or Intra Block Copy (IntraBC) mode are disclosed. At least partial pre-deblocking reconstructed video data of a current picture is stored in an on-chip buffer or cache memory. If the current block is coded using IntraBC mode, the pre-deblocking reconstructed video data of the current picture stored in the on-chip buffer or cache memory are used to derive IntraBC prediction for the current block. In some embodiments, if the current block is coded using Inter prediction mode, Inter reference video data from the previous picture stored in the on-chip buffer or cache memory are used to derive Inter prediction for the current block. In another embodiment, the motion compensation/motion estimation unit is shared by the two modes.

Abstract: A decoding apparatus has an arithmetic decoder and a controller. A counter logic of the controller generates a first statistics result according to a first syntax element decoding result. A control logic of the controller instructs the arithmetic decoder to perform a first scan procedure at least once to generate the first syntax element decoding result of transform coefficients of a transform coefficient block, controls a repetition number of a second scan procedure based at least partly on the first statistics result, and instructs the arithmetic decoder to perform the second scan procedure at least once to generate a second syntax element decoding result of the transform coefficients. The first scan procedure decodes a first coded syntax element of one transform coefficient when performed by the arithmetic decoder once. The second scan procedure decodes a second coded syntax element of one transform coefficient when performed by the arithmetic decoder once.

Abstract: An exemplary video decoding apparatus includes a first decoding unit configured for decoding a first encoded block to generate first residual values, a first detecting unit configured for detecting whether all of the first residual values have a same first value, a first processing circuit configured for processing the first residual values to generate first processed residual values, and a second processing circuit configured for generating a decoded block corresponding to the first encoded block. When all of the first residual values have the same first value, the first detecting unit controls the second processing circuit to generate the decoded block without referring to the first processed residual values.

Abstract: A video processing system includes a storage device, a demultiplexing circuit, and a syntax parser. The storage device includes a first buffer and a second buffer. The demultiplexing circuit performs a demultiplexing operation upon an input bitstream to write a video bitstream into the first buffer and write start points of bitstream segments of the video bitstream stored in the first buffer into the second buffer. Each start point is indicative of a start address of a corresponding bitstream segment stored in the first buffer. The syntax parser includes syntax parsing circuits and a syntax parsing control circuit. The syntax parsing control circuit fetches a start point from the second buffer, assigns the fetched start point to a syntax parsing circuit, and triggers the selected syntax parsing circuit to start syntax parsing of a bitstream segment that is read from the first buffer according to the fetched start point.

Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.

Abstract: A video processing system has a storage device, an audio/video demultiplexing circuit, and a video decoder. The storage device has a bitstream buffer that is a ring buffer. The audio/video demultiplexing circuit receives an input data, and performs an audio/video demultiplexing operation upon the input data to write data of a video bitstream into the ring buffer. The video decoder fetches data of the video bitstream from the ring buffer, and performs a video decoding operation upon the fetched data of the video bitstream.

Abstract: A backward adaptation apparatus includes a first storage apparatus, a count table maintenance apparatus, and a backward probability update circuit. The first storage apparatus has a first buffer and a second buffer allocated therein. The first buffer stores a first probability table involved in processing of a first frame. The second buffer stores a second probability table selectable for processing of a second frame following the first frame. The count table maintenance apparatus maintains a count table, wherein the count table maintenance apparatus has at least one count data updating circuit shared for dynamically updating the count table during the processing of the first frame. The backward probability update circuit refers to information of the count table and information of the first probability table to calculate the second probability table in the second buffer at an end of the processing of the first frame.

Abstract: A method and apparatus for deblocking process using multiple processing units are disclosed. The video image is divided into at least two regions. The in-loop filter is applied to block boundaries associated with said at least two regions using multiple processing units. The in-loop filter is re-applied to one or more second block boundaries adjacent to region edge between two regions after applying the in-loop filter to the first block boundaries adjacent to the region edge. Furthermore, at least a first portion of said applying the in-loop filter to the first block boundaries and a second portion of said applying the in-loop filter to the second block boundaries are performed concurrently. The multiple processing units may correspond to multiple processing cores within one processor chip.

Abstract: A residual processing circuit has a single-path pipeline and a single-path controller. The single-path pipeline has an inverse scan (IS) circuit, an inverse quantization (IQ) circuit and an inverse transform (IT) circuit arranged to process a current non-zero residual data block in a pipeline manner. The current non-zero residual data block is at least a portion of a transform unit. The single-path controller controls pipelined processing of the current non-zero residual data block at the single-path pipeline. The single-path controller instructs the IS circuit to start IS processing of a next non-zero residual data block before the IT circuit finishes a first half of IT processing of the current non-zero residual data block.

Abstract: A video processing apparatus includes an external storage device, a hardware entropy engine, and a software execution engine. The hardware entropy engine performs entropy processing of a current picture, and further outputs count information to the external storage device during the entropy processing of the current picture. When loaded and executed by the software execution engine, a software program instructs the software execution engine to convert the count information into count table contents, and generate a count table in the external storage device according to at least the count table contents. The count table is referenced to apply a backward adaptation to a probability table that is selectively used by the hardware entropy engine to perform entropy processing of a next picture.

Abstract: A video transmitting system includes a source buffer, a video encoder, a bitstream buffer, and a transmitting circuit. The source buffer receives pixel data of pixels of a video frame. The video encoder retrieve pixel data of a portion of the pixels of the video frame from the source buffer, and starts encoding the pixel data of the portion of the pixels before pixel data of a last pixel of the video frame is received by the source buffer. The bitstream buffer receives a network abstraction layer (NAL) stream from the video encoder, wherein the NAL stream is generated by encoding the pixel data of the portion of the pixels. The transmitting circuit retrieves the NAL stream from the bitstream buffer, and starts outputting the NAL stream before the pixel data of the last pixel of the video frame is encoded by the video encoder.

Abstract: A backward adaptation apparatus includes a first storage apparatus, a count table maintenance apparatus, and a backward probability update circuit. The first storage apparatus has a first buffer and a second buffer allocated therein. The first buffer stores a first probability table involved in processing of a first frame. The second buffer stores a second probability table selectable for processing of a second frame following the first frame. The count table maintenance apparatus maintains a count table, wherein the count table maintenance apparatus has at least one count data updating circuit shared for dynamically updating the count table during the processing of the first frame. The backward probability update circuit refers to information of the count table and information of the first probability table to calculate the second probability table in the second buffer at an end of the processing of the first frame.

Abstract: A method and apparatus of reusing reference data for video decoding are disclosed. Motion information associated with motion vectors for coded blocks processed after the current block are derived without storing decoded residuals associated with the coded blocks. Reuse information regarding reference data required for Inter prediction or Intra block copy of the coded blocks is determined based on the motion information. If the current block is coded in the Inter prediction mode or the Intra block copy mode, whether required reference data for the current block are in an internal memory is determined and the reference data are fetched from an external memory to the internal memory if the required reference data are not stored in the internal memory. The reference data in the internal memory is managed according to the reuse information to reduce data transferring between the external memory and the internal memory.

Abstract: A transmitter device includes a processing unit and a compression unit. The processing unit obtains a branch of data and partitions the branch of data into a plurality of snippets. Each snippet includes a group of data. The compression unit compresses each snippet into a plurality of packets according to value of each datum included in the corresponding snippet. The compression unit compares the value of each datum with a first threshold value to generate a first packet. The first packet includes first information indicating which data included in the corresponding snippet has the corresponding value not equal to the first threshold value. The compression unit further generates the remaining packets according to the first information.

Abstract: A count table maintenance apparatus for maintaining a count table referenced to apply a backward adaptation to a probability table. The count table maintenance apparatus includes a count data access interface, at least one buffer, and at least one count data updating circuit. The count data access interface determines a read address and a write address of the storage apparatus. The at least one buffer buffers at least one input count data, wherein the at least one input count data is derived from count data read from the count table according to the read address. The at least one count data updating circuit updates the at least one input count data read from the at least one buffer to generate at least one updated count data, and store the at least one updated count data into the storage apparatus according to the write address.

Abstract: A buffering apparatus for buffering context arrays of a multi-tile encoded picture having a plurality of tiles includes a first buffer and a second buffer. The first buffer is arranged to buffer a first context array referenced for performing entropy decoding upon a first tile of the multi-tile encoded picture. The second buffer is arranged to buffer a second context array referenced for performing entropy decoding upon a second tile of the multi-tile encoded picture. When the first tile is currently decoded according to the first context array buffered in the first buffer, the second context array is buffered in the second buffer.

Abstract: A hybrid video decoder has a hardware decoding circuit, a software decoding circuit, and a meta-data access system. The hardware decoding circuit deals with a first portion of a video decoding process for at least a portion of a frame, wherein the first portion of the video decoding process includes entropy decoding. The software decoding circuit deals with a second portion of the video decoding process. The meta-data access system manages meta data transferred between the hardware decoding circuit and the software decoding circuit.